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Title: Input/output connection arrangement for microprogrammable computer
Description: Description:
BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to microprocessors and particularly to input/output devices for providing data and/or address information to and receiving output information from a digital data processing device. 2. Description of the Prior Art Input/Output devices generally communicate with processing units over an input/output bus over which is carried data and control signals for utilization and operation of the respective devices Ordinarily, data and control information is carried upon separate buses or connecting lines and such control and data signals are usually terminated in a fixed control element or data register within the central processor. SUMMARY OF THE INVENTION According to instant invention, an input/output device is connected to a central processor by means of three buses. One is primarily used to transmit input data to the processor, a second is primarily used to transmit an address of an addressable element within the central processor, and the third to receive output data from the central processor. The instant invention provides a structure which is extremely flexible in that the bus normally used for addressing an addressable element within the processor may also be used to carry data, and neither of the input buses is terminated at a specified location. For example, data can be applied over both of the input buses, be operated upon in an arithmetic and logic unit, and then outputted to the input/output device on the third bus. Alternatively, the first bus may carry an address of a memory or register element which is addressable, and the second bus may carry data to be placed in the addressable element. Further, the address bus may provide an address of an addressable element within the processor from which information may be extracted and placed on the output bus. An object of the invention is to provide a processor in which memory operations are performed in a parallel mode. A further object of the invention is to provide a processor in which Read Only Memory operations are performed in a parallel mode. A still further object of the invention is to provide a processor with a single-phase fixed clock system. A further object of the invention is to provide a processor with a double interrupt system for both multiplexed and high speed data transfer for real time operation. A further object is to provide a microprocessor in which the control memory can branch from one program segment to another without losing a machine cycle time of the single phase clock. Another object of the invention is to provide a processor capable of extended or relative addressing of control or main memory in a single machine cycle time. A still further object of the invention is to provide a processor in which the clock is single phase and controllable by the user to allow connection of peripheral devices of varying speeds. These and other objects, features, and advantages of the invention will become more apparent when the following description is read in conjunction with the drawings, in which: FIG. 1 is an overall block diagram of the processor of the instant invention. FIG. 2 is a block diagram of the Micro Address Generator portion of the processor. FIG. 3 is a block diagram of the Microinstruction Processing portion of the processor of the instant invention. FIG. 4 is a block diagram of the Arithmetic and Logic Unit and General Register Portion of the processor. FIG. 5 is a diagram showing the information flow of the processor from a general register through a function block and back to a general register. FIG. 6 is a diagram of an alternate information flow path. FIG. 7 is a diagram of a third information flow path wherein an IO register is a source and either an IO or general register is the destination. FIG. 8 is a block diagram of the Interrupt flow of the processor. FIG. 9 is a diagram showing the locations of the micro fields in a microinstruction used by the device of the instant invention. FIG. 10 is a timing diagram showing the interrupt timing of the processor. FIG. 11 is a table describing the functions of the ALU Select field of a microinstruction. FIG. 12 is a table showing bit position assignments of the B Bus. FIG. 13 is a table describing the Microprogramming of Bus sources. FIG. 14 is a table showing Word/Byte operation of the device. FIG. 15 is a table showing the relative addressing feature of the device as represented in a microinstruction. FIG. 16 is a Timing diagram of the basic single phase clock and system clock. FIG. 17 is a logic block diagram of the address decoding logic for the processor's IO and interrupt system. FIG. 18 is a timing diagram of A Bus and B Bus timing. FIG. 19 is a timing diagram of the C Bus timing. FIG. 20 is a timing diagram of a typical multiplexed IO interrupt. FIG. 21 is a block diagram of IO modules in a multiplexed IO interrupt priority string. FIG. 22 is a logic block diagram of the IO interrupt request logic of the device of the invention. FIG. 23 is a logic block diagram of the IO device address to A Bus logic. FIG. 24 is a block diagram of an External Condition Logic Circuit. FIG. 25 is a timing diagram of External Condition timing. FIG. 26 is a block diagram of the Fast Interrupt Request and Response to/from the processor. FIG. 27 is the Fast Interrupt timing diagram for a Single Data Transfer. FIG. 28 is a Fast Interrupt timing diagram for a Multiple Data transfer. FIG. 29 is a block diagram showing essential elements of DMA. FIG. 30 is a block diagram of a Multidevice Mode arrangement of processors according to the invention. FIG. 31 is a block diagram of Priority Control Logic of the device. FIG. 32 is a block diagram of Request Control Logic. FIG. 33 is a logic block diagram of the B Bus Control Logic. FIG. 34 is a timing diagram of the Fast Interrupt Priority Control of the device. FIG. 35 is a block diagram of the IO Bus of the processor according to the invention. FIG. 36 is a block diagram showing the IO Enable Control logic. FIG. 37 is a timing diagram of the IO Active signal. FIG. 38 is a block diagram of the Multiplexer IO Interrupt. FIG. 39 is a timing diagram of a Multiplexed IO Interrupt. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT In a preferred embodiment, a microprogrammed data processor may consist of a device organized in a generalized three-bus structure where the functional processing units are interconnected between operative buses by means of tri-state logic. Tri-state logic allows each unit to either drive, receive from, or present a high impedance to the buses under control of a microcontrol register. FIG. 1 shows such an arrangement wherein the A bus, B bus and C bus are shown at 1, 2 and 3 respectively. Connecting the A bus 1 and the C bus 3 are a set of input/output registers 4 which are additionally connected to an input/output bus 6 by means of a register bus selection multiplexer 8. A set of general registers 10 is connected by means of their input to the C bus and by means of their output to the A and B buses. As shown in FIG. 1, the general registers may be 16 bits wide, with the most significant 8 bit appearing on the left side of the diagram and the least significant 8 bit appearing on the right side thereof. It is possible to utilize a block of 8 bit registers (using only the least significant 8 bits) by means of a two to one multiplexer 12 which would divide the C bus' 16 bits into two 8 bit segments. Likewise, although the diagram indicates only the least significant 8 bit segment connected to the A bus and B bus, with the optional most significant 8 bit register block the resulting 16 bit words may be directly placed on the A bus or B bus. Also shown associated with the general register block is an adder 14 connected between the B bus and the two to one multiplexer 12. The adder 14 allows an arithmetic operation to be performed upon data as it is being passed through the general register block from, for example, the B bus to the A bus. A translator 15 allows the storage of microinstruction sets corresponding to the macroinstruction instruction set of a computer to be emulated. A main memory and scratch pad memory 16 and 18, respectively, are shown connected such as to receive data from the A bus and an address from the B bus. The memory output is directed to the C bus 3. The scratch pad memory 18 may be used for intermediate storage beyond the limits of the 8 general registers or for other purposes to be described later. The main memory can be used to store data, results, microinstructions awaiting transfer to a variable control memory, or microinstructions if the device is being used in an emulation mode to emulate the macroinstruction set of another data processing machine. The microcontrol elements of the device include the micro-address register 20, the control memory 22 which may comprise a read-only memory and/or a random access memory, and the microcontrol register 24 which holds the current microinstruction while it is being executed. Also associated with the microcontrol elements are a series of multiplexers 26, 28, 30, 32, 34 and 36. The multiplexers are used primarily for translating between various address/data information bit widths. A push stack 38 and a stack pointer counter 40 also associated with the microcontrol elements and their functions will be described later. Similarly, decoder 42 will be described in conjunction with the description of the microcontrol register contents. An arithmetic and logic unit 44 with its associated input and output multiplexers 46 and 48, respectively, is capable of performing, in a preferred embodiment, 32 arithmetic or 16 logical operations, taking its two operands from the A bus and B bus and placing the results on the C bus. In very general terms, the operation of the machine is such that a 32-bit microinstruction is divided into a number of fields which control all the operations of the machine. For example, the microinstruction determines the source of data for the A bus and B bus, whether it is to be an input/output interface or a general register. It determines the function to be performed in the arithmetic and logic unit on data from the A bus and B bus, and it further determines that data from the A bus is to be stored in scratch pad/main memory at an address contained on the B bus. Complete definition of the microinstructions fields will be provided later in this specification. It is apparent, from a view of FIG. 1, that the microinstructions can direct the flow of data through a variety of paths. Incoming data from the input/output bus, for example, can be routed directly to scratch pads/main memory or can be first operated on in the arithmetic and logic unit 44. Results from the ALU 44 can be transmitted immediately by an input/output register 4 to the input/output bus 6 or can instead be held in a general register 10 pending further manipulation within the machine. Similarly, information from scratch pad/main memory (18, 16) can be routed to the input/output bus 6 or to a general register 10. The general registers 10 may be used to buffer data between the C bus 3 and the A bus 1 or B bus 2 for further processing or storage within the machine. Similarly, the ALU 44 can be used as a path to move data unchanged from the A bus 1 or B bus 2 to the C bus 3. Thus, multiple fields enable the microinstruction to control a number of operations and address civil locations simultaneously. A tightly packed microinstruction provides parallel processing and results in efficient machine utilization. It is apparent that, although not specifically shown in FIG. 1 for purposes of clarity of description, a plurality of control paths exist from the microcontrol register 24 to each of the devices which has access to one or more of the buses. It may also be noted that the generalized three-bus architeture of the device makes it possible to add functions as the needs arise, such as, a high-speed multiply/divide, square root, trigmetric functions, and code conversions. The addition of a translator 15, together with an emulation microprogram in the control memory permits the device to emulate a computer instruction set. System Organization Three types of information are existant within the system. The basic element of information is a 16-bit word in which the bit positions are numbered from 0 through 15 as follows:
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Byte 0 Byte 1
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0 1 2 3 .vertline.4 5 6 7
0 1 2 3 .vertline.4 5 6 7
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The binary information in the system is generally expressed in hexidecimal notation because four binary digits of information can be expressed by a single hexidecimal digit. Thus, a byte can be expressed with a string of two hexidecimal digits, a word with a string of four hexidecimal digits, and a double word with a string of eight hexidecimal digits. For purposes of this disclosure, a hexidecimal number is displayed as a string of hexidecimal digits surrounded by single quotation marks and preceeded by the letter X. For example, the binary number 01011010 is expressed in hexidecimal notation as X 5A. Hexidecimal numbers are generally used to denote addresses and data values. There are instances, however, in which decimals numbers are more meaningful or are customary. Also, for purposes of this disclosure, fixed-point data is expressed in two's complement notation consisting of a 15-bit integer and a sign bit in the 0 position. Logical operations assume that a logical data word format consisting of 16 bits without sign, is used. A second class of information within the system is the micro-address. The micro-address is 12 bits, capable of addressing up to 4,096 control memory locations. The micro-address register (MAR) 20, push stack 38, and related gating operations are on a 12-bit basis when a micro-address is routed over one of the three buses 1, 2, 3, it occupies the least significant 12 positions of the 16 bit positions of each bus. The third class of information in the system is the microinstruction, 32 bits in length. The control memory 22 and the microcontrol register (MCR) 24 both operate on a 32-bit basis. When a microinstruction is routed over one of the buses, it is handled into 16-bit sections. The flow of information within the device may be described in four categories called a micro-address, microinstructions, data, and interrupt. The basic microinstruction format is a 32-bit format subdivided into 11 micro-operational fields (micro OP fields) as shown below. This format will be extensively discussed in a later following section of this specification.
__________________________________________________________________________
0 31
__________________________________________________________________________
A
IO RA L RB A Bus B Bus C Bus/
Branch
Mult. Mult. Mult.
Mode Select
U Select
Cont. Cont. Regist.
Cont. uOP uOP uOP
Mode Cont. Fld. 1
Fld.
Fld.
__________________________________________________________________________
3
The micro-address information flow is shown generally in FIG. 2. Various elemental blocks are numbered to coincide with the numbers originally given in FIG. 1. Note the addition, however, of a clock control device 50 which is shown as driving the MAR 20. Although the clock control is shown for only the one element 20, the equivalent clock function is assumed to be applied in functional relation to all blocks in which the symbol .phi. appears. The micro-addresses are normally held in the MAR 20. From here they are applied at .phi. at the 4:1 memory address multiplexer 28 to select the control memory location in which a microinstruction is stored. The micro-address in the MAR 20 can be changed in two ways: 1. Incremented to the next micro-address by the clock. 2. Jumped to another micro-address supplied from the C bus. It should be noted that, for the purposes of the remainder of this specification, where a slant line with a number immediately thereunder is associated with a line on any of the figures, the number indicates the number of wires connecting the associated elements. For example, between the C bus and the micro-address register 20 a 12-wire cable is the connective element. The micro-address applied to control memory 22 can be multiplexed from 3 sources in addition to the micro-address register: A bus, B bus, and interrupt logic. The interrupt logic 52 generates micro-address corresponding to each interrupt. When an immediate address is used and it is desired merely to increment the micro-address register 20, bits 20 through 31 from the microcontrol register 24 are used directly as the next micro-address. At the same time, this immediate address is routed via bus A through the arithmetic and logic unit (ALU) 44 with a one added thereto. The result is presented via the C bus to the input of the MAR 20. The next system clock will cause this value to be put into the MAR 20 allowing continuous simultaneous fetch/execute cycles through the system. Relative micro-addressing will be discussed in some detail later in this specification. The current micro-address in the MAR 20 can be stored in the push-stack 38 and replaced with a micro-address from the C bus 3. Also, the micro-address from the push stack 38 can be routed by the C bus 3 to the micro-address register 20. At the same time the micro-address is stored in the push stack, 6 status bits are entered into the push stack. Instruction Flow The microinstructions are stored in control memory. In the instant embodiment, two types of control memory are shown, a read only memory 22 and a random access memory 23. It is also within the scope of the invention to provide additional types of control memory such as an electrically alterable memory. In addition, a separate memory may be provided to perform such functions as diagnostics and field varification. Micro-instruction processing is diagrammed in FIG. 3. When addressed by a micro-address, a microinstruction is transferred from control memory 22 or 23 via a 2 to 1 multiplexer 32 to the microcontrol register MCR 24. A microinstruction can also reach the MCR 24 from a maintenance control panel via the C bus 3 and its associated 2 to 1 multiplexer 30 in 2 16-bit increment. In the case of the random access type control memory 23, a new microinstruction can be written into the location addressed by the micro-address. The new microinstruction is obtained in two 16-bit increments from the A bus 1 over the 16-bit line shown in FIG. 3. A microinstruction can be read out from any type of control memory via a two to one multiplexer 30 in two 16-bit increments to the C bus 3. From the MCR 24, the microinstruction is decoded to provide control signals that direct the flow of data through the system as well be detailed later. The last 12 bits of the microinstruction, when used as an immediate micro-address are placed on the A bus 1 by means of the 12-bit line shown in FIG. 3. Similarly, the last 8 bits of the microinstruction, when used as an Emit field (to be discussed later) are placed on the B bus 2. The three bits defining the bit switch/position are decoded in decoder 42 and placed on the B bus. With respect to timing, the first microinstruction is read from the control memory 22, 23. When this microinstruction is clocked into the MCR 24, the incrementor (ALU 44) is activated causing the MAR 24 to be incremented to MAR+1. Since there are no phases in the clock of the device, this new address is immediately presented to the control memory 22 which reads the next microinstruction to the input of the MCR 24. The next clock will save the datum result input to the MCR 22 to the new microinstruction that was waiting and increment the MAR to MAR+1. This process continues until a micro-address other than a sequential sequence is needed. Data Flow Data flows through a number of paths and registers including the arithmetic and logic unit ALU 44, general registers 10, input/output modules of various kinds 4, scratch pad 18, main memory 16, and instruction translator 15 if such a device is used to provide emulation of computer macroinstructions. Arithmetic and Logic Unit (ALU) The ALU 44 accepts a byte or word from the A bus and B bus, performs arithmetic or logic operations on the two operands and outputs the results through a rotat/byte select logic 48 to the C bus 3 as shown in FIG. 4. Operand word or byte selection, operations selection, and output shift or byte select are all specified by control signals derived from the microinstruction to be described later. The input byte select gate 46a, 46b applies both bytes, the left byte, or right byte, from the A bus to the A operand or from the B bus to the B operand. The arithmetic or logic operations is specified by the mode signal M (shown above as the first of the 11 microoperational fields). One of 16 arithmetical and logic operations is selected by the four select lines (shown as the second and fourth microoperational fields of the diagram). Carry in, Cn, adds "one" the results. The ALU result can be shifted left or right one bit or transferred direct to the C bus. Also, the right byte of the results can be placed in the left byte of the C bus. General Registers The general registers 10 provide a source for the A bus 1 and B bus 2 and the destination for the C bus 3, as shown in FIG. 4. For example, the A and B operands for the ALU 44 can be taken from general registers 10 and the ALU results can be stored in a general register. Additionally, one can be added to or subtracted from the value on the B bus and the result stored in one of the general registers. This function is performed by the add/subtract one function 14 connected from the B bus through the 2 to 1 multiplexer 12 through a one to eight demultiplexer and ultimately applied to the general register 10. Status Four of the six status bit to the ALU 44 are derived from arithmetic operations, as defined below. Carry: In word operation, the carry-out from the most significant bit of the ALU (Bit 0) or, in byte operation, the carry-out from the most significant bit of the byte (bit 8). Overflow: An arithmetic operation on A and B operands results in a number greater than the largest number that can be processed in the space specified (word or byte). For example, in addition, overflow occurs if the sum of two positive numbers is negative or the sum of two negative numbers is positive, using two's complement format. Similarly, in subtraction, overflow results if the subtraction of a negative number from a positive number gives a negative number or if the subtraction of a positive from a negative number gives a positive number. The overflow is indicated as a status bit in register 62. C bus equals 0: All bits of the C bus are 0. This status bit is carried in register 60. Sign: In word operation, the most significant bit of the word (bit 0) or, in byte operation, the most significant bit of the byte (bit 8). This status is carried in register 58. Control Mode: A command decoded from the microinstructions sets and resets this bit. It is used for additional control of an optional function such as a macroinstruction translator. This register is not diagramed in FIG. 4. Input/Output Input/output modules 4 may be of various types to handle various modules such as a teletype or paper tape. In general, the modules perform functions of the following types: 1. Accept incoming data and place it on the A bus. 2. Transfer outgoing data from the C bus to the output. 3. Accept multiplexed general interrupts and place their identification on the A bus. The input/output will be extensively discussed in a latter portion of this specification. Scratch Pads/Main Memory Referring to FIG. 1, data is written from the A bus into the scratch pad 18, main memory 16, at the location addressed by the B bus. Data is read to the C bus 3 from the scratch pad 18, main memory 16 location addressed by the B bus. Translator The translator 15 enables the device to emulate a computer instruction set. This provides the means for translating a macroinstruction, taken from the C bus into a micro-address .phi., placed on the A bus, that accessed the first of a series of microinstructions in control memory 22 to implement the macroinstruction. Moreover, in the case of a macroinstruction containing an argument field, such as the address field used in calculating direct or indirect memory locations, the translator transfers the argument field to the B bus. Maintenance Control Panel The maintenance control panel (not shown) provides controls and indicators that display the current status of the machine and make changes in that status. The controls permit 16 data bits to be placed on the C bus, in the microcontrol register, or (12 bits) in the micro-address register. Interrupt and status bits are displayed continuously. Register or bus contents can be displayed one at a time. The maintenance control panel will be further defined in detail in a later section. Information Flow: Summary Information flow is the path which data takes from a general register through some function lock back to a general register. A simplified view of this flow is shown in FIG. 5. The first level of gating (multiplexers 56) selects which register is to be gated to the source buses A and B. The second level of gating (byte select gates 46a, 46b,) selects which byte on the A and B buses is to be presented to the ALU 44 to have some function performed. The third level of gating (shift/byte select 48) selects whether the output of the ALU 44 is to be logically shifted left or right one bit position and/or if the right byte should be moved to the left byte of the C bus (destination bus). Adding to this information flow is an alternate path that data may take instead of through the ALU function logic. This alternate path is shown in FIG. 6. In FIG. 6, the first level of gating (multiplexers 56) select which register is to be used as the data register (A and C buses) and which register is to be used as the memory address register (B bus). The second level of gating and the third level of gating are both disabled (disconnected through the used of the tri-state logic previously discussed) so that the output of the main memory can be connected directly to the C bus (register destination bus). The third information path allowed is shown in FIG. 7. The first level of gating for the A bus (multiplexers 56) select, instead of a general register 10 as its source, an IO register 4 to be gated onto the A bus. The first level of gating for the B bus is free to select a general register to be gated to the B bus. The data flow can then be routed to the main memory 16 through the ALU 44 back to either the IO register 4 or general register 10 or from the main memory 16 to the IO register 4. The third level of gating 48 is used only when the ALU function is active. Interrupt Flow Seven interrupt lines originate in various parts of the system, as shown in FIG. 8, all of which terminate at an interrupt register 70 when one or more of the interrupt flip-flops is set, the micro-address of the interrupt that has the highest priority is applied through the interrupt micro-address and coder 52 to the memory address multiplexer 28 which then addressed the control memory 22. The interrupts are diagramed in FIG. 8 in order of priority from X 4 to X A. Each microaddress points to a microinstruction specified by the system programmer initiating a procedure that responds to that interrupt. The contents of the interrupt register may be displayed on a maintenance control panel 66. The interrupts form the following functions: Power Off: A logic signal from the power supply that indicates loss of input power which in a short period of time after input power has dropped. Power supply may be designed such that there is sufficient storage in the power supply such that the voltage does not go out of regulation until some period of time beyond that which the interrupt is activated. Power On: A logic signal from the power supply that indicates the power is on. Fast Interrupt One: A logic signal from the input/output interface 4 directly to the interrupt register and used primarily for high-speed data transfers to/from user logic via the IO interface 4 from/to scratch pad/main memory 16, 18. The interrupt register returns a hardware response to the IO interface. Fast Interrupt Two: The same as fast interrupt one, except of lower priority. One of the fast interrupts may be used to input data while the other is used to output data. The fast interrupts will be described in details in the later section: Input/Output: A logic signal that indicates that a multiplexed input/output interrupt is pending on one or more of the input/output interfaces. In response to the signal, the system programmer requests the highest priority I/O module 4 with an interrupt pending to put its address on the A bus. Error: A logic signal that indicates a parity error has occured in control memory, scratch pad or main memory. Auto Load: A switch signal from the maintenance control panel used to indicate an automatic loading routine. This signal defects a trap to control memory location as a function of whether the system is on or off. This may also be used as a console interrupt. MICROINSTRUCTION REPERTIORE This section describes the actions that results from each microoperations code at each field of the microinstruction. As earlier discussed, the microinstruction consists of 32 bits, divided into a number of single-purpose and multi-purpose shields. FIG. 9 shows the possible combinations of fields in a single 32 microinstruction. As can be seen from the figure, up to 11 fields may be defined in a single microinstruction. These fields are decoded the microinstruction decoder 42, (FIG. 1) to provide control signals for all other elements of the system. The microprogram is stored in control memory 22. During the execution of a particular microinstruction, that microinstruction is held in the microcontrol register MCR 24. The configuration shown in FIG. 9 may be sumarized in the following statements:
Bus,
A(0-15) A Bus
A(0-7) Left Byte, A Bus
A(8-15) Right Byte, A Bus
B(0-15) B Bus
B(0-7) Left Byte, B Bus
B(8-15) Right Byte, B Bus
C(0-15) C Bus
C(0-7) Left Byte, C Bus
C(8-15) Right Byte, C Bus
IO(0-15) Input/Output Bus
IO(0-7) Left Byte, IO Bus
IO(8-15) Right Byte, IO Bus
Register,
IORn(0-15) Input/Output Register 0 - 7
GRn(0-15) General Register 0 - 7
MAR(0-11) Micro Address Register
MCR(0-31) Micro Control Register
IR(0-6) Interrupt Register
SR(0-6) Status Register
PSn(0-17) Push Stack 0 - 15
T(0-15) Translator
Memory,
Control Memory, CM-RAM(MAM)
= CM(0-1024, 0-31)
CM-ROM(MAM) = CM(0-4096, 0-31)
CM-EARDM(MAM) = CM(0-4096, 0-31)
Field Verification, FV(MAM)
= CM(x`FOO`-x`FFF`, 0-31)
Scratch Pad, SP(B)
= SP(0-1024, 0-15)
Main Memory, MM(B)
= MM(0-65,536, 0-15)
Clock, Phi or .phi.
One-phase clock (one clock
dropped for main memory accesses)
Other Terms:
ALU Arithmetic Logic Unit
ALU-A A operand inputs to ALU
ALU-B B operand inputs to ALU
ALUM ALU Mode
ARG Argument from Translator
Cn Carry-in to ALU
DA Device Address
I Interrupt
IOI Input/Output Interrupt
IOM IO Mode
MAM Memory Address Multiplexer
MCP Maintenance Control Panel
S Status bit
Vn Vector n from Translator (a micro
address)
SINGLE PURPOSE MICRO FIELDS The specific function, taken alone, of each single-field micro opcode is defined. Unless otherwise stated, execution of each micro instruction occupies one clock period and each microinstruction updates the status register. Input/Output Mode: Input/Output Mode (IOM) selects general registers 10 or input/output data 4. RA Select: When IO Mode is false, RA Select is the address of a general register 10 which is to be the source of data for the A bus. When IO Mode is true, RA Select and Device Select (bits 28-31 of the microinstruction) are the address of an input/output module 4 which is to be the source of data for the A bus. (Unless specifically inhibited, this field sources a general register or input/output module to the A bus). A bus control is needed to complete the selection process. ALU Mode: ALU Mode causes the Arithmetic Logic Unit 44 to perform arithmetic functions when false and logic functions when true. This mode is discussed further in connection with ALU Select. RB Select: RB Select is the address of a general register 4 which is to be the source of data for the B bus. In addition, when IOM is true and B bus control is 3, the RB Select field assigns a bit to one of the eight least significant positions on the B bus, as discussed further in the section entitled Bit Switch/Position. B bus control is necessary to complete the selection process. A Bus Control: A Bus Control is concerned with the source of data placed on the A bus, the bytes applied to the A operand inputs of the ALU 44, and the bytes read from or written into main memory 16. O Contents of general register 10 or input/output module 4 data specified by IO Mode, RA Select and Device Select are placed on A bus. Both bytes of A bus are applied to A operand of ALU 44. Both bytes of A bus may be read from or written into main memory 16. If IOM = O then A(0-15).rarw.GRn(0-15) else A(0-15).rarw.IOn(0-15) ALU-A(0-15).rarw.A(0-15) If Branch Control = x'2' then C(0-15).rarw.MM(0-15) (B) If Branch Control = x'3' then MM(0-15) (B).rarw.A(0-15) 1. Contents of general register 10 or input/output module 4 data specified by IO Mode, RA Select and Device Address are placed on A bus. The left byte of A bus is applied to the A operand of ALU, right justified. The left byte of A bus may be read from or written into the left byte of main memory 16. If IOM=O then A(0-15).rarw.GRN(0-15) else A(0-15).rarw.IOn(0-15) ALU-A(8-15).rarw.A(0-7); ALU-A(0-7).rarw.0 If Branch Control = x'2' then C(0-7).rarw.MM(0-7)(B) If Branch Control = x'3' then MM(0-7)(B).rarw.(0-7) 2. Contents of general register 10 or input/output module 4 data specified by IO Mode, RA Select, and Device/Select are placed on the A bus. The right byte of A bus is applied to the A operand of ALU, right justified. The right byte of A bus may be read from or written into the right byte of main memory 16. If IOM = O then A(0-15).rarw.GRn(0-15) else A(0-15).rarw.IOn(0-15) ALU-A(8-15).rarw.A(8-15); ALU-A(0-7).rarw.0 If Branch Control = x'2' then C(8-15).rarw.MM(8-15)(B) If Branch Control = x'3' then MM(8-15)(B).rarw.A(8-15) 3. Contents of Micro Address Register 20 are placed on the A bus, right justified. Both bytes of A bus are applied to the A operand of ALU 44. Transferring a register 10 to the A bus is inhibited. A(4-15).rarw.MAR(0-11); ALU--A(0-15).rarw.A(0-15) A micro opcode in one of the C bus/register control micro opcodes is needed to complete A bus control. A bus control can be overridden by MCR 24 Control: = x'3', Read Vector 1 to A Bus from Translator 15, MCR Control = x'5', Read Vector 2 to A Bus from Translator 15, MCR Control = x'E', Read Interrupt Address to A bus, and C Bus/Register Control = x'B', Immediate Addressing Invoked to MAR. B Bus Control: B bus control is concerned with the source of data placed on the B bus and the bytes applied to the B operand inputs of the ALU 44. 0 Contents of general register 10 specified by RB Select are placed on B bus; both bytes of B bus 90 to ALU 44. B(0-15).rarw.grn(0-15) Alu-b(0-15).rarw.b(0-15) 1. contents of general register 10 specified by RB Select are placed on the B bus; the left byte of B bus goes to ALU 44, right justified. B(0-15).rarw.grn(0-15) Alu-b(8-15).rarw.b(0-7) alu-b(0-7).rarw.0 2. contents of general register 10 specified by RB Select are placed on the B bus; the right bytes of B bus go to ALU 44, right justified. B(0-15).rarw.grn(0-15) Alu-b(8-15).rarw.b(8-15) alu-b(0-7).rarw.0 3. if IOM is false, the Emit Field is transferred to the B bus, right justified. If IOM is true, a one is transferred to the position in the right byte of the B bus defined by RB Select, as discussed further in the section entitled Bit Switch/Position. In either case, the right byte of B bus is applied to ALU 44, right justified. If IOM = O then B(8-15).rarw.MCR (24-31) else B(8-15).rarw.1(RB Sel) In either case: ALU-B(8-15).rarw.B(8-15) ALU-B(0-7).rarw.0 The B bus control can be overridden by MCR Control = x'7', Read Argument to B bus from Translator 15. C Bus/Register Control: The C bus/register control field is concerned primarily with routing data from the C bus to the general register 10 or input/output modules 4. This field is concerned also with shifting left or right one position of the ALU 44 output to the C bus, with applying the value on the C bus to the micro-address register 20, with incrementiong/decrementing the value on the B bus and returning it to a general register 10, and with using the last twelve bits of the microinstruction as an immediate address. In the case of transfers from the C bus to the general registers 10 or input/output modules 4 defined by IO mode, RA Select, and Device Select, the bytes transferred are controlled by A bus control. In the case of transfers from the C bus to general registers 10 selected by RB Select, the bytes transferred are controlled by B bus control. Transfers from the general registers 10 or input/output modules 4 to the A bus are not affected by the C bus/register control = x'B' inhibits transfers to the A bus, since the A bus is being used by the immediate address. For other values of the C bus/register control field, transfers from the general registers or input/output modules to the A bus are always enabled. Moreover, transfers from the general registers 10 to the B bus are not affected by the C bus/register control field. In other words, these transfers are always enabled, so far as this field is concerned. C Bus/Register Control Function: x'0' No strobe to any register. Data from the C bus is not transferred into a general register 10, input/output module 4 or any other register. However, transfers from a general register or an input/output module to the A bus and from a general register to the B bus can take place. (Transfers from a general register to the A bus can be inhibited by the C bus/register control field, but not enabled.) C(0-15).rarw.alu(0-15) x'1'C Bus to MAR. Transfers the least significant 12 bits on the C bus to the micro-address register 20 on the clock following the micro opcode. The status register is not updated, but its contents are maintained. Then the microinstruction corresponding to the micro-address transferred into the MAR 20 is transferred into the microcontrol register 24 on the second check following the micro opcode and is available for execution during the third clock period. Thus, execution of this micro opcode occupies two clock periods. C(0-15).rarw.alu(0-15) mar(0-11).rarw.c(4-15).phin Mam(0-11).rarw.mar(0-11) mcr(0-31).rarw.cm(0-31)(mamo-11).phin+1 Status Register: The foregoing micro opcode is the first one encountered in which the status register (part of the maintenance control panel 66) was not updated. As a general rule, the status register is updated by the clock concluding each microinstruction period. Under the circumstances enumerated below, however, the status register is not updated and the existing contents are maintained. In brief, it may be said that the contents of the status register are unchanged when branching or jumping to a new micro-address. In detail: a. The C bus/register control field of the current microinstruction equals x'1' or x'9', involving C bus to MAR 20, or b. The branch control field of the current microinstruction specified a Test/Branch micro opcode or Push, or c. A fast interrupt micro instruction in control memory location x'006' or x'007' is being executed. x'2' Use RA Select Device Select, IO Mode, and A bus control as a routing address. If A bus control = 1, the right byte of the ALU output is transferred to the left byte of the C bus; for other values of A bus control, both bytes of ALU output are transferred to the C bus. For A bus control = 0, both bytes of the C bus are transferred to a general register or input/output module selected by IO mode, RA Select, and Device/Select; for A bus control = 1, the left byte of the C bus is transferred to register 10; for A bus control = 2, the right byte of the C bus is transferred to register 10; for A bus control = 3, both bytes of the C bus to general register 10, and C(8-15).rarw.0 If A bus Con = 1 then C(0-7).rarw.ALU(8-15) else C(0-15).rarw.alu(0-15) a bus Control 0: If IOM = 0 then GRn(0-15).rarw.C(0-15) else Ion(0-15).rarw.C(0-15) 1. if IOM = 0 then GRn(0-7).rarw.C(0-7) else Ion(0-7).rarw.C(0-7) 2. if IOM = 0 then GRn(8-15).rarw.C(8-15) else Ion(8-15).rarw.C(8-15) 3. grn(0-15).rarw.C(0-15) x'3' Use RB Select and B bus control as a routing address. If B bus control = 1, the right byte of ALU 44 output is transferred to the left byte of the C bus; for other values of B bus control, both bytes of ALU output are transferred to general register 10 addressed by RB Select; for B bus control = 1, the left byte of C bus is transferred to a general register 10; for B bus control = 2, the right byte of the C bus is transferred to a general register 10. If B bus Con = 1 then C(0-7).rarw.alu(8-15), c(8-15).rarw.0 else C(0-15).rarw.alu(0-15) b bus Control: 0: GRn(0-15).rarw.C(0-15) 1: grn(0-7).rarw.C(0-7) 2: grn(8-15).rarw.C(8-15) 3: grn(0-15).rarw.C(0-15) x'4' Shift ALU output (to C bus) one bit to the left, and use RA Select, Device Select, IO Mode, and A bus control as the routing address. If A bus control = 1, the right byte of ALU 114 output is shifted one bit to the left, the least significant bit is filed with zero, and is transferred to left byte of C bus. The left byte of C bus is transferred to the left byte of general register 10 or input/output module addressed 4 by IO Mode, RA Select, and Device Select. For other values of A bus control, both bytes of ALU output are shifted one bit to the left, the least significant bit is filed with zero, and both bytes are transferred to the C bus. For A bus control - 0, both bytes of C bus are transferred to a general register 10 or input/output module 4. For A bus control = 3, both bytes of C bus are transferred to a general register. If A Bus Con = 1 then C(0-6).rarw.alu(9-15), c7.rarw.0, c(8-14).rarw.alu(9-15), c15.rarw.0, else C(0-14).rarw.alu(1-15), c15.rarw.0 a bus Control: 0: If IOM = 0 then Grn(0-14).rarw.C(0-14), Grn15.rarw.C15(=0) else Ion(0-14).rarw.C(0-14), Ion15.rarw.C15(=0) 1: if IOM = 0 then Grn(0-6).rarw.C(0-6), Grn7.rarw.C7(=0) else Ion(0-6).rarw.C(0-6), Ion7.rarw.C7(=0) 2: if IOM = 0 then Grn(8-14).rarw.C(8-14), Grn15.rarw.C15(=0) else Ion(8-14).rarw.C(8-14), Ion15.rarw.C15(=0) 3: grn(0-15).rarw.C(0-15) x'5' Shift ALU output (to C bus) one bit to the left, and use RB Select and B bus control as a routing address. If B bus control = 1, the right byte of ALU output is shifted one bit to the left, the least significant bit is filled with zero, and is transferred to the left byte of C bus; for other values of B bus control, both bytes of ALU output are shifted one bit to the left, the least significant bit is filed with zero, and both bytes are transferred to C bus. For B bus control = 0 or 3, both bytes of the C bus are transferred to the general register addressed by RB select; for B bus control = 1, the left byte of the C bus is transferred to a general register; for B bus control = 2, the right byte of the C bus is transferred to a general register. If B bus Con = 1 then C(0-6).rarw.alu(9-15), c7.rarw.0 c(8-14).rarw.alu(9-15), c15.rarw.0 else C(0-14).rarw.alu(1-15), c15.rarw.0 if B bus Con = 3 then Grn(0-14).rarw.C(0-14), Grn15.rarw.C15(=0) If B bus Con = 1 then Grn(0-6).rarw.C(0-6), Grn7.rarw.C7(=0) If B bus con = 2 then Grn(8-14).rarw.C(8-14), Grn15.rarw.C15(=0) x'6' Shift ALU output (to C Bus) one bit to the right and use RA Select, Device Select, IO Mode, and A bus control as routing address. If A bus control = 0, both bytes of ALU output are shifted one bit to the right, the most significant bit is filed with zero, and both bytes are transferred to C bus; both bytes of the C bus are transferred to a general register or input/output module addressed by IO Mode, RA Select, and Device Select. If A bus Control = 1, the ALU output is shifted one bit to the right and the right byte of output is transferred to the left byte of the C bus; the left byte of the C bus is transferred into a register. In byte operation, since the inputs to the ALU A and B operands are limited to the right byte, output bit 7 will usually be zero, but may be one if the operation performed results in a carry. For A bus control = 2, the right byte of ALU output is shifted one bit to the right, the most significant bit is filed with zero, and transferred to the right byte of C bus; the right byte of C bus is transferred into register. In this case, the carry to bit 7, if any, from the ALU output are shifted one bit to the right, the most significant bit is filed with zero, and both bytes are transferred to the C bus, and both types of the C bus are transferred to a general register. A Bus Control: O: c(1-15).rarw.alu(0-14), co.rarw.0 if IOM = 0 then Grn(0-15).rarw.C(0-15) else Ion(0-15).rarw.C(0-15) 1: If B bus Control = 0 then C(0-7).rarw.alu(7-14), c(8-15).rarw.alu(7-14) else C(0-7).rarw.alu(7-14), c8.rarw.0, c(9-15).rarw.alu(8-14) if IOM = 0 then Grn(0-7).rarw.C(0-7) else Ion(0-7).rarw.C(0-7) 2: CO.rarw.0, C(1-7).rarw.ALU(0-6).rarw.C8.rarw.0, C(9-15).rarw.ALU(8-14) If IOM = 0 then Grn(0-15).rarw.C(8-15) else Ion(8-15).rarw.C(8-15) 3: CO.rarw.0, C(1-15).rarw.ALU(0-14) GRn(0-15).rarw.C(0-15) x'7' Shift ALU Output (to C bus) one bit to the right, and use RB Select and B bus control as a routing address. If B bus control = 0, both bytes of the ALU output are styled one bit to the right, the most significant bit is filed with zero, and both bytes are transferred to the C bus; both bytes of C bus are transferred to the general register addressed by RB Select. If B bus control = 1, the ALU output is shifted one bit to the right and the right byte of the output is transferred to the left byte of the C bus; the left byte of the C bus is transferred into the general register addressed by RB Select. In byte operation, since the inputs to the ALU A and B operands are limited to the right byte, output bit 7 will usually be zero, but may be one if the operation performed results in a carry. If B bus Control = 2, the right byte of the ALU output is shifted one bit to the right, the most significant bit is filed with zero, and the right byte is transferred to the C bus; the right byte of the C bus is transferred into the general register addressed by RB Select. If B Bus control = 3, each byte is shifted one bit to the right, the most significant bit of each byte is filed with zero, and both bytes are transferred to the C bus; both bytes from the C bus are transferred to the general register addressed by RB Select. B Bus Control: 0: CO.rarw.0, C(1-15).rarw.ALU(0-14) GRn(0-15).rarw.C(0-15) 1: If A bus control = 0 or 3 then C(0-7).rarw.ALU(7-14) and C(8-15).rarw.ALU(7-14) else C(0-7).rarw.ALU(7-14) and C8.rarw.0 and C(9-15).rarw.ALU(8-14) GRn(0-7).rarw.C(0-7) 2: CO.rarw.0, C(1-7).rarw.ALU(0-6), C8.rarw.0, C(9-15).rarw.ALU(8-14) GRn(8-15).rarw.C(8-15) 3: CO.rarw.0, C(1-7).rarw.ALU(0-6), C8.rarw.0, C(9-15).rarw.ALU(8-14) GRn(0-15).rarw.C(0-15) x'8' Increment B bus and place result in RB Selected register. This field adds one to the bit value on the B bus and places the result in the general register addressed by RB Select. Both bytes of the ALU output are transferred directly to the C bus. Grn(0-15).rarw.B(0-15) plus 1 C(0-15).rarw.alu(0-15) x'9' Increment B bus and place result in RB Selected general register. C bus to MAR. See x'1' and x'8' for detailed description. This micro opcode occupies two clock periods. x'A' Increment B bus and place result in general register addressed by RB select. Use IO Mode, RA Select, Device Select, and A bus control as a routing address. Grn(0-15).rarw.B(0-15) plus 1 (Remaining operations same as x'2') x'B' Immediate Address. The source of the Immediate Address placed on the A bus can be one of four: 1. If IO Mode is false, the Immediate Address field of the microinstruction. 2. If IO Mode is true, the Device Address for the highest priority input/output device controller that has a multiplexed IO interrupt pending. 3. If IO Mode is false, Branch Control is x'1', and MCR Control is x'3', Vector 1 micro-address from the (optional) Translator. 4. If IO Mode is false, Branch Control is x'1', and MCR Control is x'5', Vector 2 micro-address from the (optional) Translator. The remaining operations are common. The operations are described in detail below. If IOM = 0, bits 20-31 of the microinstruction, called the immediate address, are transferred from the microcontrol register to the A bus. If IOM = 1, the input/output module with a multiplexed IO interrupt pending that has the highest priority location places its Device Address (consisting of the RA Select and Device Select values) on the A bus, as follows:
0 1 2 3 4 5 6 7 89 10 11 12 13 14 15
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1RA Sel Device
Select
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The input/output module provides a signal forcing bit 8 to 1, in effect, adding 128 to the Device Address. At the same time, the contents of the ALU Select field, bits 20-23 of the microinstruction are appended to the above to generate a 12-bit micro-address as follows:
0 1 2 3 456789 10 11 12 13 14 15
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xxxxALU Sel1Device Address A Bus
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If IOM = 0, Branch Control = x'1', and MCR = x'3' or x'5', the Translator places the Vector 1 or Vector 2 microaddresses on the A bus. In each case, a 12-bit micro-address is now present on the A bus. This micro-address via the memory address multiplexer 28 addresses a location in control memory during the clock period of the micro opcode. At the same time, the 12 bits are applied to the A operand inputs of the ALU 44, incremented by one, transferred direct to the C bus, and applied to the micro-address register 20 at the clock following the micro opcode. Thus, the incremented micro-address serves as the control memory address during the following clock cycle. In the execution of this micro opcode, although the ALU Select field constitutes part of the Immediate Address or expanded Device Address, the ALU 44 is forced to execute the function A plus 1 by the hardware. The A bus sources are summarized as follows: If IOM = 0 then A(4-15).rarw.mcr(20-31) else A(9-15).rarw.da a8.rarw.1 a(4-7).rarw.mcr(20-23) if IOM = 0, BRC = x'1', MCR = x'3' then A(4-15).rarw.v1(0-11) if IOM = 0, BRC = x'1', MCR = x'5' then A(4-15).rarw.v2(0-11) the remaining operations are common to all sources: Mam(0-11).rarw.a(4-15) alu(0-15).rarw.a(4-15) plus 1 C(0-15).rarw.alu(0-15) mar(0-11).rarw.c(4-15).phin Both the different and common operations are executed in one clock cycle. See also the section entitled Immediate Addressing. x'C' Increment B bus and place result in general register addressed by the RB Select; shift ALU output (to C bus) one bit to the left; use RA Select, Device Select, IO Mode, and A bus control as the routing address. Grn(0-15).rarw.B(0-15) plus 1 (Remaining operations same as x'4') x'D' Not assigned. x'E' Increment B bus and place result in general register addressed by RB Select; shift ALU output (to C bus) one bit to the right; use RA Select, Device Sheet, IO Mode, and A bus control as the routing address. Grn(0-15).rarw.B(0-15) plus 1 (Remaining operations same as x'6') x'F' Decrement B bus and place result in general register addressed by RB Select; use RA Select, Device Select, IO Mode, and A bus control as the routing address. Grn(0-15).rarw.B(0-15) minus 1 (Remaining operations same as x'2') Branch Control: The branch control field is concerned primarily with Test/Branch micro opcodes. In general, a Test/Branch micro opcode tests a condition, external or internal, and branches to an immediate address or a relative address as the next control memory location is found. Otherwise, the next micro-address in sequence is taken as the control memory location. Addressing and Branching will be later discussed. In addition, the Branch Control field is concerned with arithmetic operations, reading or writing scratch pad/main memory, push stack operations, and status bits. As discussed generally in a previous paragraph entitled Status Register, certain Branch Control micro opcodes cause the status bits to be loaded into the status register. In the case of other Branch Control micro opcodes, the current status bits are not loaded, but those in the status register are retained. The effect of each Branch Control micro opcode on the status register is included in the statements of function below. Branch Control Function: x'O' Normal Mode Carry False. In arithmetic Mode (ALU Mode = 0), the ALU performs the operations listed under Cn = 0, ALU Select. Status bits are loaded into the status register at the next clock, providing C bus/register control is not x'1' or x'9'. C.rarw.alu cn = 0 Sr.rarw.s.phin (PHI = Clock) x'1' Normal Mode Carry True. In arithmetic mode (ALU Mode = 0), the ALU performs the operations listed under Cn = 1, ALU Select. Status bits are loaded into the status register at the next clock, providing C bus/register control is not x'1' or x'9'. C.rarw.alu cn = 1 Sr.rarw.s.phin x'2' Read Scratch Pad or Main Memory. The contents of the SP/MM location addressed by B bus are read out to the C Bus. Status bits are loaded into the status register at the next clock, providing C bus/register control is not x'1' or x'9'. In the case of main memory the bytes read out are specified by A bus control. C(0-15).rarw.sp(0-15)(b) sr.rarw.s.phin A bus Control 0: C(0-15).rarw.MM(0-15)(B) 1: c(0-7).rarw.mm(0-7)(b) 2: c(8-15).rarw.mm(8-15)(b) 3: c(0-15).rarw.mm(0-15)(b) this micro opcode requires one clock period for scratch pad and a double-length clock period for main memory. x'3' Write Scratch Pad or Main Memory. The bits on the A bus are written into the Scratch Pad/Main Memory location addressed by the B bus. Because the C bus is not used, the values of the status bits derived from the C bus (though loaded into the status register) are indeterminate. In the case of main memory the bytes written are specified by A bus control. Sp(0-15)(b).rarw.a(0-15) sr.rarw.s.phin A Bus Control 0: MM(0-15)(B).rarw.A(0-15) 1: mm(0-7)(b).rarw.a(0-7) 2: mm(8-15)(b).rarw.a(8-15) 3: mm(0-15)(b).rarw.a(0-15) this micro opcode requires one clock period for scratch pad and a double-length clock period for main memory. x'4' Test/Branch on External Condition Set. Address external line (or lines) on IO module 4 defined by RA Select and Device Select. If the test is successfel, the least significant 12 bits of the C bus are loaded into the MAR 20 on the clock following the micro opcode. The status register is not modified. The micro instruction corresponding to the micro address transferred into the MAR 20 is transferred into the microcontrol register 24 on the second clock following the micro opcode and is available for execution during the third clock period. Execution time is two clock cycles. If the test is unsuccessful, the micro-address register 20 increments to the next micro-address in sequence at the first clock. Under this circumstance, execution time is one clock cycle. If EXT = 1 then Mar(0-11).rarw.c(4-15).phin Mcr(0-31).rarw.0.phin Mam(0-11).rarw.mar(0-11) mcr(0-31).rarw.cm(0-31)(mamo-11).phin+1 else MAR plus 1 at PHIn Because the Device Select field is employed in addressing the extermal lines (requiring that C bus/register control be other than x'B'), the immediate address field can not be used to supply the new address. x'5' Test/Branch on External Condition Reset. Same as x'4' except that the test state is reversed. x'6' Push. Stores 12-bit micro-address form micro address register 20 and six status bits from status register in 18-push stack 38. The contents of the C bus are transferred to the MAR.20 to serve as the next micro address. The status register is not modified. Other operations depend upon the C bus/register control field. If C bus/register control is x'B', the immediate address obtained from the last 12 bits of the microcontrol register 24 or the device address supplied by an input/output module 4 requesting service provides the micro-address that addresses control memory 22. Thus, Push with Immediate Address occupies one clock period. If C bus/register Control is not x'B', the microcontrol register 24 resets at the first clock, so that no operations are executed during the following clock period. The micro-address transferred into the MAR 20 from the C bus addresses the microinstruction transferred into the microcontrol register 24 on the second clock. This microinstruction is available for execution during the third clock period. Thus, Push without Immediate Address occupies two clock periods. Ps(0-11).rarw.mar(0-11) ps(12-17).rarw.sr(0-5) sr unchanged If CB/RC = 'B' then A(4-15).rarw.mcr(20-31) + da mam(0-11).rarw.a(4-15) c(0-15).rarw.a(4-15) plus 1 Mar(0-11).rarw.c(4-15).phin If CB/RC = x'B' then Mar(0-11).rarw.c(4-15).phin Mcr(0-31).rarw.o.phin Mam(0-11).rarw.mar(0-11) mcr(0-31).rarw.cm(0-31)(mamo-11).phin+1 Interrupts: The use of a Push function (and also a Pull function) in processing an interrupt is shown in FIG. 10. It is assumed that an Interrupt Request goes true during the clock cycle in which microinstruction x, for example, is being executed. The next clock sets the Interrupt flipflop, synchronizing the Interrupt Request. The Interrupt flipflop leads to a jump to a control memory location (in this example, x'008') in which the IO Interrupt microinstruction is stored. This microinstruction is assumed to contain Push and Immediate Address commands, the effect of which is to place micro-address R on the memory address multiplexer (shown at 1 on FIG. 10.) On the next clock, micro-address R moves to the microcontrol register and is executed. At the same time, the IO Interrupts are disabled. The interrupt routine, R, R+1, R+2, . . . R+n, R+n+1, is next executed. The R+n microinstruction contains an IO Control micro opcode commanding the IO module to drop the Interrupt Request (2). The R+n+1 microinstruction contains a Pull Command, discussed in the next paragraph (3). At this time the Enable IO Interrupt status bit from the push stack restores the original IO Interrupt Enable status. x'7' Pull. The micro-address from the last-used push-stack location is transferred via the C bus to the microaddress register 20 on the first clock. The status bits from the last-used push-stack location are transferred into the status register at the same time. The microinstruction corresponding to the micro-address transferred into the MAR is transferred into the microcontrol register on the second clock and is available for execution during the third clock period. The micro-address register increments to the next micro-address in sequence on the second clock. This microopcode occupies two clock periods. C(4-15).rarw.ps(0-11) sr(0-5).rarw.ps(12-17).phin Mar(0-11).rarw.c(4-15).phin Mcr(0-31).rarw.o.phin Mam(0-11).rarw.mar(0-11) mcr(0-31).rarw.cm(0-31)(mamo-11).phin+1 Mar plus 1 at PHIn+1 x'8' Test/Branch Overflow = 1. Examines the state of the Overflow bit in the status register. If this test is successful, the value on the C bus is placed in the MAR 20 to serve as the micro-address. If unsuccessful, the MAR increments to the next micro-address in sequence. The value on the C bus depends upon the C bus/register control function. C bus/register control is not x'B': If the test is successful, the least significant 12 bits of the C bus are loaded into the MAR20 on the clock following the microopcode. The status register is not modified. The microinstruction corresponding to the micro-address transferred into the MAR is transferred into the microcontrol register 24 on the second clock following the micro opcode and is available for execution during the third clock period. This procedure occupies two clock periods. If the test is unsuccessful, the micro-address register 20 increments to the next micro-address in sequence at the first clock. Under these circumstances, the micro opcode occupies one clock period. If OV = 1 and CB/RC = x'B' then Mar(0-11).rarw.c(4-15).phin Mcr(0-31).rarw.0.phin Mam(0-11).rarw.mar(0- Other info: Inventors: Garlic, Richard A. (Irvine, CA, US) Application Number: 428597 Filing Date: 1973-12-16 Publication_date: 1976-02-10 Assignee: Xerox Corporation (Stamford, CT) Primary Class(es): 710/48 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Shaw, Gareth D. Assistant Examiner: Thomas, James D. Attorney: Ralabate; James J., Weiss; Franklyn C., Sarli; Anthony J. |
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