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Title: Hardware/firmware communication line adapter
Claims: What is claimed is: 1. A hardware/firmware communication control logic system for accommodting the concurrent bidirectional transfer of data messages between a communications processor and different terminal devices via a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing said data messages and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means in electrical communication with said memory means and responsive to stored control information received from said communicatons processor for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) interface logic means in electrical communication with said microprocessor logic control means and said firmware control means for supplying interrupt service requests and control information to said communications processor, said communications channel, and said control logic system; and (e) said firmware control means operating in response to said control information from said processor to adapt the functions of said control logic system to the requirements of said different terminal devices. 2. A hardware/firmware communication control logic system for accommodating the concurrent bidirectional transfer of data messages between a communications processor and a communication line, which comprises: (a) first memory means in electrical communication with said communications processor for storing control and data information; (b) second memory means in electrical communication with said communications processor for storing status and data information; (c) processor decoder means responsive to said communications processor for issuing commands to control the writing of control and data information into said first memory means, and the reading of data and status information from said second memory means; (d) interrupt control logic means in electrical communication with said comunications processor and said processor decoder means for issuing interrupts to request data, control and status information from said communications processor; (e) logic resynchronization means in electrical communication with said processor decoder means for initializing said control logic system to receive data information from said communication line; (f) microprocessor means in electrical communication with said first and said second memory for serializing data from said communications processor and deserializing data from said communication line; (g) firmware control store memory means in electrical communication with said microprocessor means, and said first and said second memory means for controlling the operation of said control logic system; (h) address counter means responsive to said communications processor for addressing said firmware control store memory means to provide a sequence of microinstructions; (i) firmware instruction decoder means in electrical communication with said microprocessor means and said firmware control store memory means for controlling the writing of data into said second memory means, the loading of data into said mircoprocessor means, and the updating of said address counter means; (j) microprogram subcommand generator means responsive to said firmware control store memory means and said firmware instruction decoder means for controlling the operation of said interrupt control logic means and said logic resynchronization means; (k) multiplexer means responsive to said firmware control store memory means and in electrical communication with said microprocessor means, said interrupt control logic means and said logic resynchronization means for controlling the modification of microinstructions in said firmware instruction decoder means; (1) communication line interface logic means in electrical communication with said microprocessor means, said microprogram subcommand generator means and said communication line for signalling the occurrence of a transmit data bit or a receive data bit to said multiplexer means; (m) line control logic means responsive to said processor decoder means and said communications processor for supplying control signals to said communication line, said resynchronization means, and said interrupt control logic means. 3. A hardware/firmware comunication control logic system for accommodating the concurrent bidirectional transfer of message data between a communications processor and a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing message data to be transmitted to said channel and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means responsive to said communications processor and in electrical communication with said memory means for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) underrun means for providing a no data indication; (e) means responsive to said firmware control means for actuating said underrun means when said memory means is emptied of message data during a transmit operation; and (f) means responsive to said underrun means for signalling said communications processor of an underrun condition prior to the transfer of additional message data from said processor. 4. A hardware/firmware communication control logic system for accommodating the concurrent bidirectional transfer of message data between a communications processor and a communication channel which comprises: (a) memory means in electrical communication with said communications processor for storing said message data and status and control information exchanged between said communications processor and said control logic system; (b) firmware control means responsive to said communications processor and in electrical communication with said memory means for supplying microinstruction sequences to control the operation of said control logic system; (c) microprocessor logic control means in electrical communication with said firmware control means and said memory means for modifying said microinstruction sequences and serializing and deserializing said data messages; (d) receive means controlled by said firmware control means for receiving message data from said communication channel and transferring said data to said memory means and then to said communications processor; (e) overrun means for providing a data present indication; (f) means responsive to said firmware control means for actuating said overrun means when said memory contains message data which has not been transferred to said communications processor; and (g) further means responsive to said firmware control means for signalling said communications processor of an overrun condition if said overrun means is actuated when said receive means is operated to transfer data to said memory means. Other info: Inventors: Raymond, James C. (Framingham, MA, US) Lemay, Richard A. (Bolton, MA, US) Kelly, Richard P. (Nashua, NH, US) Application Number: 911635 Filing Date: 1978-06-01 Publication_date: 1981-03-03 Assignee: Honeywell Information Systems Inc. (Waltham, MA) Primary Class(es): 710/63 379/93.01, 710/72 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Zache, Raulfe B. Assistant Examiner: Attorney: Lester; Gerald E., Prasinos; Nicholas, Reiling; Ronald T. |
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