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Title: Spread beam computational hardware for digital beam controllers
Claims: I claim: 1. In a spread beam computational section of a digital beam controller for an electronically controlled phased array radar system including a linear computational portion for computing a plurality of groups of a predetermined number of intermediate phase command digital words corresponding to a desired spread beam radar pattern, each intermediate phase command digital word having a predetermined primary number of bits and a predetermined residue number of bits; and a non-linear computational portion for computing a spread beam phase command digital word from each computed group of said intermediate phase command digital words which have been digitally rounded off, the improvement of an apparatus for digitally rounding off each computed group of intermediate phase command digital words comprising: a random number generator for randomly generating digital words sized in relation to the predetermined residue number of bits of said computed intermediate phase command digital words; means for digitally adding a digital word randomly generated from said random number generator to the predetermined residue bits of said computed intermediate phase command digital words in each computed group to generate a corresponding plurality of groups of resultant digital words; and means for truncating the resultant digital words of each group to said predetermined primary number of bits and for providing each group of truncated resultant digital words to said non-linear computational portion of said beam spreading computational section. 2. Digital rounding off apparatus in accordance with claim 1 wherein the digital adding means includes a digital adder for each of the predetermined number of intermediate phase command words in the computed groups, said digital adder adding a randomly generated digital word to the predetermined residue number of bits of said intermediate phase command words of each computed group; and wherein the output word of each digital adder is truncated to said predetermined primary number of bits prior to being provided to said non-linear computational portion. 3. Digital rounding off apparatus in accordance with claim 1 wherein the random number generator comprises: at least one read only memory having addressably accessible registers programmed with digital words which are randomly organized in accordance with a consecutive addressing pattern of said registers; and means for addressing said at least one read only memory in a consecutive pattern to render a random generation pattern of digital words from said at least one read only memory. 4. Digital rounding off apparatus in accordance with claim 3 wherein the addressing means is a digital counter. 5. Digital rounding off apparatus in accordance with claim 1 wherein each randomly generated digital word is sized to a portion of the residue number of bits of the intermediate phase command digital word. 6. Digital rounding off apparatus in accordance with claim 5 wherein the randomly generated digital word is added to the upper most significant bits of the predetermined residue number of bits of the intermediate phase command digital word. 7. Digital rounding off apparatus in accordance with claim 5 wherein the intermediate phase command digital words are each at least 16 bits; wherein the predetermined primary number of bits is the most significant 8 bits of each intermediate phase command digital word; wherein the predetermined residue number of bits is the least significant at least 8 bits of each intermediate phase command digital word; and wherein the randomly generated digital words are each 4 bits and are added to the 4 most significant bits of the predetermined residue at least 8 bits of each intermediate phase command digital word. 8. Digital rounding off apparatus in accordance with claim 1 wherein each computed group contains a pair of intermediate phase command digital words. 9. In a spread beam computational section of a digital beam controller for an electronically controlled phased array radar system including a linear computational portion for computing a plurality of pairs of intermediate phase command digital words, each having a primary number of bits and residue number of bits; and a non-linear computational portion for computing a spread beam phase command digital word from each of said computed pairs of intermediate phase command digital words which have been digitally rounded off, the improvement of an apparatus for digitally rounding off each computed pair of intermediate phase command digital words comprising: a random number generator for randomly generating digital words sized to a portion of the residue number of bits of said computed intermediate phase command digital words; means for digitally adding to the upper most significant bit portion of the residue number of bits of each computed pair of intermediate phase command digital words, a digital word randomly generated from said random number generator to generate a plurality of resultant pairs of digital words; and means for truncating each resultant pair of digital words to said primary number of bits and for providing each truncated pair of digital words to said non-linear computational portion of said beam spreading computational section. 10. Digital rounding off apparatus in accordance with claim 9 wherein the computed intermediate phase command words are each at least 16 bits; wherein the primary number of bits is the 8 most significant bits and the residue number of bits is the at least 8 least significant bits; and wherein the randomly generated digital words are each 4 bits which are added to the 4 most significant bits of the residue at least 8 bits of each computed pair of intermediate phase command digital words. Other info: Inventors: Smith, Winthrop W. (Maitland, FL, US) Application Number: 964565 Filing Date: 1978-11-29 Publication_date: 1980-10-21 Assignee: Westinghouse Electric Corp. (Pittsburgh, PA) Primary Class(es): 342/377 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Blum, Theodore M. Assistant Examiner: Attorney: Zitelli; W. E. |
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