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Title: Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes
Claims: What is claimed is: 1. A data processing system including a microprogrammable data processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different phases of operation to completion, said data processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to said multibit operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a multibit control sequence code having less bits than said operation code and an address, said control sequence code specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences; a cycled addressable second control store including a plurality of locations for storing at least one microinstruction of a different one of said plurality of execution sequences; an address register connected to receive said address from said first control store and connected to said second control store for read out of the microinstruction contents of a location during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation; hardwired control state sequencing means coupled to said first control store including sequence decoder circuit means for decoding said control sequence codes, said hardwired control sequencing means for generating different sequences of control signals for defining the different operations to be performed during a first one of said phases of operation for each instruction, said hardwired control sequencing means, being conditioned by each control sequence code within a certain class read out in response to the operation code of an instruction being processed, for generating a predetermined one of said different sequences of control signals, for performing said operations during said first one of said phases of said instruction, for transferring said address into said address register, for continued processing of said instruction under the control of the specified one of said plurality of execution sequences, and for placing said sequencing means in a predetermined state, said specified execution sequence including a microinstruction containing a restart code bit pattern; and, decoder circuit means coupled to said hardwired control state sequencing means and to said output register, said decoder circuit means being operative upon the read out of said microinstruction restart code pattern from said second control store into said output register to generate signals for switching said hardwired control state sequencing means from said predetermined state to another state to continue instruction processing in said pipelined fashion. 2. The system of claim 1 wherein said hardwired sequence control means includes: a plurality of bistable elements coupled to said sequence decoder circuit means, said plurality of bistable elements being conditioned by said sequence decoder circuit means to switch states for generating said different sequences of control signals and said decoder circuit means in response to said each control sequence code switching a predetermined one of said plurality of bistable elements to a binary ONE corresponding to an escape state. 3. The system of claim 1 wherein said restart code contains a first coded bit pattern, said decoder circuit means being conditioned by said first coded bit pattern to generate signals for switching said hardwired control state sequencing means from said predetermined state to one of a plurality of states for loading the next instruction to be processed into said first one of said registers. 4. The system of claim 3 wherein said one of said plurality of states is selected in accordance with the coding of said sequence control code and status signals corresponding to certain conditions. 5. The system of claim 4 wherein said system further includes buffer storage apparatus coupled to said processing unit for providing fast access to instructions and data stored therein, first, second, third and fourth ones of said bistable elements designated FXRPT, FPI-INIT, FPIM-1 and FPOA respectively being coupled to receive signals corresponding to said first coded bit pattern representative of a type 1 restart, said first, second, third and fourth bistable elements being conditioned to switch to a binary ONE in accordance with the following expressions: FXRPT=XED+RPTS; fpi-init=xed+rpts.multidot.str-cpr; fpim-1=xed+rpts.multidot.str-cpr.multidot.ibuf-emty; and, FPOA=XED+RPT.multidot.STR-CPR.multidot.IBUF-EMTY wherein the terms XED and RPTS designate that the instruction being processed is an execute double or repeat respectively as indicated by said control sequence code while the terms STR-CPR and IBUF-EMTY designate the presence of a store compare condition and buffer empty condition respectively indicated by said status signals. 6. The system of claim 4 wherein said microinstruction containing said restart code bit pattern is included within a predetermined point within said specified execution sequence so as to provide no breaks within said number of different phases of operation. 7. The system of claim 6 wherein said instruction includes at least one address, said system further including buffer storage apparatus coupled to said processing unit for providing fast access to instructions and data stored therein and said different phases of operation including an instruction cycle (I cycle) wherein an instruction operand address is generated, a cache cycle(C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction operand address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said data processing unit, said predetermined point within said specified execution sequence occurring at a time which corresponds to two cycles prior to the completion of the execution of said instruction during said E cycle. 8. The system of claim 1 wherein said system further includes buffer storage apparatus coupled to said processing unit for providing fast access to data and instructions stored therein, said restart code containing a second coded bit pattern, said decoder circuit means being conditioned by said second coded bit pattern to generate signals for switching said hardwired control state sequencing means from said predetermined state corresponding to an escape state to said another state corresponding to a first of a number of states, said hardwired control state sequencing means including means for generating signals during said number of states for conditioning said buffer storage apparatus to fetch blocks of instructions automatically under hardwired control to enable said processing unit to begin processing of a new block of instructions. 9. The system of claim 1 wherein said restart code contains a third coded bit pattern, said decoder circuit means being conditioned by said third bit pattern to generate signals for switching said hardwired control state sequencing means from said predetermined state corresponding to an escape state to said another state corresponding to an initial state, said hardwired sequencing means generating other predetermined ones of said different sequences of control signals in accordance with the codings of other control sequence codes read out from said first control store in response to the operation codes of successive instructions as stored in said first one of said plurality of registers for performing operations during certain ones of said phases in parallel with the read out of microinstructions from said second control store. 10. The system of claim 9 wherein said specified execution sequence includes a last microinstruction containing another restart code bit pattern, said hardwired sequencing means stopping the generating of further sequences of control signals after a predetermined time interval, said second control store continuing the successive read out of microinstructions including said last microinstruction of said specified execution sequence into said output register and said decoder circuit means being conditioned by said another restart code bit pattern to generate signals for releasing said hardwired sequencing means from a last current state to a next state for continuing the processing of further instructions. 11. A data processing system including a microprogrammable data processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different phases of operation to completion, said data processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code at least one address and a tag field coded for specifying the type address modification to be performed upon said address; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to said multibit operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a multibit control sequence code having less bits than said operation code and an address, said control sequence code specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences; a cycled addressable second control store including a plurality of locations for storing at least one microinstruction of a different one of said plurality of execution sequences and microinstructions of a number of address modification routines; an address register connected to receive said address from said first control store and connected to said second control store for read out of the microinstruction contents of a location during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation; control flag indicator circuit means coupled to said first one of said plurality of registers, and to said second control store, said control flag indicator circuit means in response to a predetermined coding of said tag field to generate an output control signal indicative of a predetermined type of address modification; hardwired control state sequencing means coupled to said first control store and to said control flag indicator circuit means, including sequence decoder circuit means for decoding said control sequence codes, said hardwired control sequencing means for generating different sequences of control signals for defining the different operations to be performed during a first one of said phase of operation for each instruction, said hardwired control sequencing means, being conditioned by each control sequence code within a certain class read out in response to the operation code of an instruction being processed and being further conditioned by said control signal, for generating a predetermined one of said different sequences of control signals resulting in said sequencing means being switched to a state, for performing of an address development operation under microprogram control, and for transferring control to one of said address modification routines for generation of an effective address, said one address modification routine including a last microinstruction containing a restart code bit pattern; and, decoder circuit means coupled to said hardwired control state sequencing means and to said output register, said decoder circuit means being operative upon the read out of said microinstruction restart code pattern from said second control store into said output register to generate signals for switching said hardwired control state sequencing means from said predetermined state to another state to continue the processing of said instruction in said pipelined fashion. 12. The system of claim 11 wherein said restart code contains a fourth coded bit pattern, said decoder circuit means being conditioned by said second coded bit pattern to generate signals for switching said hardwired control state sequencing means from said predetermined state to an initial control state, said hardwired control sequencing means being operative to generate a predetermined one of said different sequences of control signals for completing the operations of first and second phases and for transferring control to one of said plurality of execution sequences specified by the address read out in response to said instruction operation code for completion of a third phase of operation. 13. A data processing system including a microprogrammable data processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different phases of operation to completion, said data processing unit comprising: a plurality of registers for storing instructions to be processed, certain ones of said instructions corresponding to multiword instructions, each including a multibit operation code, a plurality of addresses and a corresponding number of operand modification fields, at least one of said operand modification fields being coded to specify that the operand associated therewith is of a predetermined characteristic; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to said multibit operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a multibit control sequence code having less bits than said operation code and an address, said control sequence code specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences; a cycled addressable second control store including a plurality of locations for storing at least one microinstruction of a different one of said plurality of execution sequences and microinstructions of a number of operand address processing routines; an address register connected to receive said address from said first control store and connected to said second control store for read out of the microinstruction contents of a location during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation; control flag indicator circuit means coupled to said first one of said plurality of registers, and to said second control store, said control flag indicator circuit means in response to a predetermined coding of said tag field to generate an output control signal indicative of a predetermined type of address modification; hardwired control state sequencing means coupled to said first control store and to said control flag indicator circuit means including sequence decoder circuit means for decoding said control sequence codes, said hardwired control sequencing means for generating different sequences of control signals for defining the different operations to be performed during a first one of said phase of operation for each instruction, said hardwired control sequencing means, being conditioned by each control sequence code within a certain class read out in response to the operation code of an instruction being processed and being further conditioned by said control signal, for generating a predetermined one of said different sequences of control signals, for transferring said address into said address register, for continued processing of said instruction under the control of a specified one of said plurality of execution sequences, and for placing said sequencing means in a predetermined state, said specified execution sequence including as a first microinstruction one coded to test the states of signals generated by said control flag indicator circuit means, said second control store being conditioned by said first microinstruction to branch to one of said operand address processing routines, said one operand address processing routine including a last microinstruction containing a restart code bit pattern; and, decoder circuit means coupled to said hardwired control state sequencing means and to said output register, said decoder circuit means being operative upon the read out of said microinstruction restart code pattern from said second control store into said output register to generate signals for switching said hardwired control state sequencing means from said predetermined state to another state within said predetermined sequence of control signals to continue the processing of said multiword instruction in said pipelined fashion. 14. The system of claim 13 wherein said hardwired control state sequencing means is conditioned to generate control signals for completing said predetermined sequence so as to continue the processing of the remaining ones of said plurality of addresses under hardwired control. 15. The system of claim 14 wherein said hardwired sequence control means includes: a plurality of bistable elements coupled to said sequence decoder circuit means, said plurality of bistable elements being conditioned by said sequence decoder circuit means to switch states for generating said different sequences of control signals and said decoder circuit means in response to said each control sequence code of said predetermined class switching a predetermined one of said plurality of bistable elements to a binary ONE corresponding to an escape state. 16. The system of claim 15 wherein said restart code contains a fifth coded bit pattern, said decoder circuit means being conditioned by said first coded bit pattern to generate signals for switching said hardwired control state sequencing means from said predetermined state to one of a plurality of states for continuing the processing of said multiword instruction. 17. The system of claim 16 wherein said one of said plurality of states is selected in accordance with the coding of said sequence control code. 18. The system of claim 17 wherein said system further includes buffer storage apparatus coupled to said processing unit for providing fast access to instructions and data stored therein and said different phases of operation including an instruction cycle (I cycle) wherein one of said instruction operand addresses is generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said one instruction operand address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said instruction operands are executed by said data processing unit. 19. A data processing system comprising: an addressable main store having a plurality of word locations for storing information including data and instructions; a cache unit coupled to said main store for providing immediate access to data and instructions fetched from said main store, said cache unit having a plurality of addressable locations and including control means for fetching information from said main store; and, a microprogrammable data processing unit coupled to said cache unit, said microprogrammable data processing unit for performing data manipulations under the control of instructions wherein the processing of instructions proceed in a pipelined fashion wherein each instruction is processed in a number of different phases of operation to completion, said data processing unit comprising: a plurality of registers for storing instructions to be processed, each instruction including a multibit operation code; a first addressable control store coupled to a first one of said plurality of registers for receiving signals corresponding to said multibit operation code of an instruction to be processed, said first control store including a plurality of locations, each for storing a word including at least a multibit control sequence code having less bits than said operation code and an address, said control sequence code specifying one of a number of hardwired control sequences and said address identifying a first microinstruction of a different one of a plurality of execution sequences; a cycled addressable second control store including a plurality of locations for storing at least one microinstruction of a different one of said plurality of execution sequences and microinstructions of a number of operand address processing routines; an address register connected to receive said address from said first control store and connected to said second control store for read out of the microinstruction contents of a location during a cycle of operation; an output register connected to said second control store for temporarily storing said microinstruction contents read out during said cycle of operation; hardwired control state sequencing means coupled to said first control store, said hardwired control sequencing means for generating different sequences of control signals for defining the different operations to be performed during first and second ones of said phases of operation for each instruction, said hardwired control sequencing means including: sequence decoder circuit means coupled to said first control store for decoding said control sequence codes; a plurality of bistable elements coupled to said sequence decoder circuit means, said plurality of bistable elements being conditioned by said sequence decoder circuit means to switch states for generating said different sequences of control signals, and said decoder circuit means in response to said each control sequence code within a certain class for switching a predetermined one of said plurality of bistable elements to a binary ONE state and transferring said address into said address register for continued processing of said instruction under the control of a specified one of said plurality of execution sequences, said specified execution sequence including a microinstruction containing a restart code bit pattern; and, decoder circuit means coupled to said hardwired control state sequencing means and to said output register, said decoder circuit means being operative upon the read out of said microinstruction restart code pattern from said second control store into said output register to generate signals for switching said predetermined one of said plurality of bistable elements to a binary ZERO state and another one of said bistable elements to said binary ONE state to continue the processing of said instruction. 20. The system of claim 19 wherein said restart code contains a first coded bit pattern, said decoder circuit means being conditioned by said first coded bit pattern to generate signals for switching said another one of said bistable elements to said binary ONE state for loading the next instruction to be processed into said first one of said registers. 21. The system of claim 20 wherein said one of said another one of said plurality of bistable elements is selected in accordance with the coding of said sequence control code and status signals corresponding to certain conditions. 22. The system of claim 21 wherein first, second, third and fourth ones of said bistable elements designated FXRPT, FPI-INIT, FPIM-1 and FPOA respectively being coupled to receive signals corresponding to said first coded bit pattern representative of a type 1 restart, said first, second, third and fourth bistable elements being conditioned to switch to a binary ONE in accordance with the following expressions: FXRPT=XED+RPTS; fpi-init=xed+rpts.multidot.str-cpr; fpim-1=xed+rpts.multidot.str-cpr.multidot.ibuf-emty; and, FPOA=XED+RPT.multidot.STR-CPR.multidot.IBUF-EMTY wherein the terms XED and RPTS designate that the instruction being processed is an execute double or repeat respectively as indicated by said control sequence code while the terms STR-CPR and IBUF-EMPTY designate the presence of a store compare condition and buffer empty condition respectively indicated by said status signals. 23. The system of claim 22 wherein said mircoinstruction containing said restart code bit pattern is included within a predetermined point within said specified execution sequence so as to provide no breaks within said number of different phases of operation. 24. The system of claim 23 wherein each instruction includes at least one address, said system further including buffer storage apparatus coupled to said processing unit for providing fast access to instructions and data stored therein and said different phases of operation including an instruction cycle (I cycle) wherein an instruction operand address is generated, a cache cycle (C cycle) wherein said buffer storage apparatus fetches an operand specified by said instruction operand address and an execution cycle (E cycle) wherein the manipulations specified by the instruction operation code to be performed upon said operand are executed by said data processing unit, said predetermined point within said specified execution sequence occurring at a time which corresponds to two cycles prior to the completion of the execution of said instruction during said E cycle. 25. The system of claim 19 wherein said restart code contains a third coded bit pattern, said decoder circuit means being conditioned by said third bit pattern to generate signals for switching said one of said plurality of bistable elements from said binary ONE state corresponding to an escape state to a binary ZERO state and another one of said bistable elements to a binary ONE state corresponding to an initial state, said plurality of bistable elements generating another predetermined one of said different sequences of control signals in accordance with the coding of a next control sequence code read out from said first control store in response to the operation code of a next instruction stored in said first one of said plurality of registers for performing operations during certain ones of said phases in parallel with the read out of microinstructions from said second control store. 26. The system of claim 25 wherein said specified execution sequence includes a last microinstruction containing another restart code including a fourth bit pattern, said plurality of bistable elements being inhibited from further switching after a predetermined time interval, said second control store continuing the successive read out of microinstructions including said last microinstruction of said specified execution sequence into said output register and said decoder circuit means being conditioned by said another restart code bit pattern to generate a release signal for enabling said plurality of bistable elements for switching, said another bistable element switching to a binary ZERO state while a different one of said plurality of bistable elements switches to a binary ONE state for continuing the processing of further instructions. Other info: Inventors: Wilhite, John E. (Glendale, AZ, US) Application Number: 853981 Filing Date: 1977-11-22 Publication_date: 1979-07-10 Assignee: Honeywell Information Systems Inc. (Waltham, MA) Primary Class(es): 712/232 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Shaw, Gareth D. Assistant Examiner: Rhoads, Jan E. Attorney: Driscoll; Faith F., Prasinos; Nicholas, Reiling; Ronald T. |
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