Title: Firmware/hardware system for testing interface logic of a data processing system

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Claims: What is claimed is:

1. A method of testing bus interface logic electrically coupling a system unit having a firmware control system to a common communication bus in a data processing system having plural system units including a main memory unit, which comprises:

a. generating within said system unit an incorrect parity code and loading said incorrect parity code into output address registers of said system unit;

b. loading under firmware control predetermined data and a main memory address stored in said firmware control system respectively into output data registers and said output address registers of said system unit;

c. under firmware control issuing a bus cycle request and unloading said output data registers and said output address registers on said common bus, thereby supplying said main memory address with said incorrect parity code to said common bus to avoid intervening communications from said main memory unit;

d. generating from said system unit an acknowledgement of said main memory address with said incorrect parity code to initiate a loading of said predetermined data and said main memory address respectively into input data registers and input address registers of said system unit; and

e. comparing in an arithmetic unit within said system unit and under firmware control said predetermined data and said main memory address with the contents of said input data registers and said input address registers to detect interface logic errors.

2. A test system wholly contained within a system unit for testing through normal information paths the operability of interface logic electrically coupling said system unit with a common communication bus in a data processing system having plural system units including a main memory unit, said system unit having both an input and an output data storage means and an input and an output address storage means, which comprises:

a. firmware control means for loading predetermined data into said output data storage means and a main memory address into said output address storage means for transfer to said common bus;

b. parity generating means responsive to said firmware control system for providing an incorrect parity code to said output address storage means, thereby accommodating the combination of said incorrect parity code with said main memory address to avoid intervening communications from said main memory unit;

c. logic gating means in electrical communication with said firmware control means for generating to said common bus an acknowledgement of a non-occurring response by said main memory unit to said main memory address, thereby accommodating the loading of said predetermined data and said main memory address under firmware control from said common bus respectively to said input data storage means and said input address storage means; and

d. logic compare means responsive to said firmware control means for sensing an equivalence between said input and said output data storage means, and between said input and said output address storage means.

3. The combination set forth in claim 2, wherein said parity generating means includes:

a. a flip-flop responsive to said firmware control means; and

b. a parity generator in electrical communication with said flip-flop for providing said incorrect parity code.

4. The combination set forth in claim 2, wherein said logic gating means includes:

a. a NAND gate responsive to said firmware control means; and

b. a NOR gate in electrical communication with said NAND gate for supplying an acknowledgement signal to said common bus.

5. A method of controlling the flow of binary coded information through normal information paths between a system unit having a firmware control system and a command communication bus in a data processing system having plural system units including a main memory unit electrically coupled to said common bus, and verifying the operability of interface logic electrically coupling said system unit with said common bus which comprises:

a. generating within said system unit a false recognition code and loading said false code under firmware control into output address registers of said system unit;

b. loading under firmware control predetermined data and a main memory address from said firmware control system respectively into output data registers and said output address registers of said system unit;

c. generating from said system unit an acknowledgement of said main memory address with said false code to gate said output data registers and said output address registers respectively into input data registers and input address registers of said system unit; and

d. comparing in an arithmetic unit within said system unit and under firmware control said predetermined data and said main memory address respectively with the contents of said input data registers and said input address registers to detect interface logic errors.
Other info:

Inventors: Getson, Jr., Edward F. (Lynn, MA, US)
Cassarino, Jr., Frank V. (Weston, MA, US)

Application Number: 821939
Filing Date: 1977-08-04
Publication_date: 1979-06-26
Assignee: Honeywell Information Systems Inc. (Waltham, MA)
Primary Class(es): 714/43 714/32
Other Classes:
US Patent Ref:

3576541	Apr, 1971	Kwan et al.	364/200.
3579199	May, 1971	Anderson et al.	364/200.
4048481	Sep, 1977	Baile, Jr. et al.	364/200.

Other Refs:
Primary Examiner: Nusbaum, Mark E.
Assistant Examiner: Heckler, Thomas M.
Attorney: Lester; Gerald E., Prasinos; Nicholas, Reiling; Ronald T.