|
PatentVote.com: Vote on your favourite invention!
|
|
 |
Title: Process management structures and hardware/firmware control
Claims: What is claimed is: 1. In a multiprogramming computer system CPU, communicating with said main memory and said registers said multiprogramming computer system including a plurality of processes stored in said main memory, and a plurality of queues also stored in said main memory, (i.e. a process being and ordered series of instructions), each of said plurality of said processes having a predetermined priority number with respect to others of said processes and wherein a selected one of said processes is running (i.e. in control of said CPU), with selected others of said plurality of processes being in a ready state (i.e. in condition to obtain control of said CPU) and with information relative to said ready processes being stored in a ready-queue of said plurality of queues, each of said queues located at a starting location in said main memory designated as a queue head the head queue of said ready queue identifying a first process of said plurality of processes, on a basis of the priority number and FIFO arrangement, first in line for control of said CPU, a management unit for resolving priority between the running process and a process activated for CPU utilization comprising: (a) a plurality of first means, predetermined ones being associated with predetermined ones of said processes (i.e. one each of said first means being associated with one each of said processes), each of said first means for storing signals representing the priority number to its associated process for indicating priority for control of said CPU in relation to other processes in contention for said CPU; (b) second means for storing signals representing an address location of said ready process first-in-line for control of said CPU; (c) means responsive to said second means for loading one of said registers with said address location; (d) third means in said second means for storing signals representing the address of the head of said ready-queue. (e) means responsive to said third means for addressing said ready-queue; (f) fourth means in said head of said ready-queue for storing signals representing the priority number of said first process first-in-line for control of said CPU; and (g) fifth means communicating with said first, second, third and fourth means for comparing the signals representing the priority number of said running process with the signals representing the priority number of said first process first-in-line for control of said CPU whereby the higher priority between said running process and said first process is determined. 2. The combination as recited in claim 1 wherein said ready-queue is comprised of process links having a predetermined format each process link being associated with a selected one of said others of said plurality of processes, said process links being arranged in said ready-queue in accordance to a FIFO (first-in-first-out) priority. 3. The combination as recited in claim 2 including in each of said process links sixth means for storing signals indicating an address for said process associated with said process link. 4. The combination as recited in claim 3 including in each of said process links seventh means for storing signals indicating a priority number for said process associated with said process link. 5. The combination as recited in claim 4 including in each of said process links eighth means for storing signals indicating an address of the process link next in line in the queue of ready processes. 6. In a multiprogram computer system comprising at least a virtual memory for storing a plurality of processes, and including a plurality of queues, a central processing unit (CPU) communicating with said virtual memory, said CPU having a control unit for providing signals for controlling said CPU, a plurality of address, general and base registers communicating with said virtual memory for storing information relating to a native mode of operation of said CPU, a plurality of scientific registers communicating with said virtual memory for storing information relating to a secientific mode of operation of said CPU, and instruction-counter register communicating with said virtual memory for storing the address of the next instruction to be executed by said CPU, and a status register also communicating with said virtual memory for storing information relating to the status of said CPU, said computer system further having an operating system for supervising and scheduling the execution of said processes, with a selected one of said processes (CJP) being in a running state (i.e. currently controlling said CPU), with selected others of said processes being in a ready state (i.e. in condition to obtain control of said CPU) and being arranged sequentially for control of said CPU by a ready-queue on a basis of a priority number and FIFO (first-in-first-out) arrangement, said ready queue being stored in a group of locations in said virtual memory, the start of which is designated as the queue head, the priority number being a predetermined number assigned to each process on the basis of relative importance to others of said processes the queue head of said ready-queue identifying a first process first in line for control of said CPU, a process management unit for managing said queue of processes comprising: (a) a plurality of first means, predetermined ones being associated with predetermined ones of said processes (i.e. one each of said first means being associated with one each of said processes), each of said first means for storing signals representing associated information available to its associated process for controlling said CPU when selected in accordance to the priority number to be in a running state; (b) second means for storing signals indicating an address of said running process (CJP); (c) means responsive to said second means for unloading said address, general and base registers of said address and associated information of said running process; (d) third means in said second means for storing signals indicating an address of the head of said ready-queue; (e) means responsive to said third means for addressing said ready-queue; and, (f) fourth means communicating with said first, second and third means and responsive to signals from said control unit for "rolling out" said running process (CJP) (i.e. removing said running process from being in control of said CPU) when said selected one of said CJP processes has terminated its execution. 7. The combination as recited in claim 6 including fifth means in said first means responsive to a first signal from said control unit for storing the contents of said general registers. 8. The combination as recited in claim 7 including sixth means in said first means responsive to a second signal from said control unit for storing the contents of said base registers. 9. The combination as recited in claim 8 including seventh means in said first means responsive to a third signal from said control unit for storing the contents of said scientific registers. 10. The combination as recited in claim 9 including eighth means in said first means responsive to a fourth signal from said control unit for storing the contents of said instruction-counter register. 11. The combination as recited in claim 10 including ninth means in said first means responsive to a fifth signal from said control unit for storing the contents of said status register. 12. In a multiprogram computer system comprising at least a virtual memory for storing a plurality of processes and including a plurality of queues, a central processing unit CPU communicating with said virtual memory, said CPU having a control unit for providing signals for controlling said CPU, a plurality of address, general and base registers communicating with said virtual memory for storing signals of information relating to a native mode of operation of said CPU, a plurality of scientific registers communicating with said virtual memory for storing signals of information relating to a scientific mode of operation of said CPU, an instruction-counter register communicating with said virtual memory for storing signals indicating the address of the next instruction to be executed by said CPU, and a status register also communicating with said virtual memory for storing signals of information relating to the status of said CPU, said computer system further having an operating system for supervising and scheduling the execution of said processes, with a selected one of said processes (CJP) being in a running state (i.e. currently controlling said CPU), with selected others of said processes being in a ready state (i.e. in condition to obtain control of said CPU) and being arranged sequentially for control of said CPU by a ready-queue on a basis of a priority number and FIFO (first-in-first-out) arrangement, said ready queue being stored in a group of locations in said virtual memory, the start of which is designated as the queue head, the priority number being a predetermined number assigned to each process on the basis of relative importance to others of said processes the queue head of said ready-queue identifying a first process first in line for control of said CPU, a process management system for managing said processes comprising: (a) a plurality of first means, predetermined ones being associated with predetermined ones of said processes (i.e. one each of said first means being associated with one each of said processes), each of said first means for storing signals indicative of information available to its associated process for controlling said CPU when selected to be in a running state; (b) second means communicating with said operating system and with said processes for storing signals indicative of associated information available to said processes; (c) means responsive to said second means for providing said information to said processes; (d) third means in said second means for storing signals of an address of the head of said ready-queue; (e) means responsive to said second means for loading said address, general and base registers with said address and associated information of said running process CJP; (f) fourth means in said head of said ready-queue for storing signals of a priority number to said first process first-in-line for control of said CPU; and, (g) fifth means communicating with said first, second, third and fourth means and responsive to signals from said control unit for "rolling in" the process (NJP) identified by said head of said ready queue (i.e. giving control of said CPU to said NJP) after said selected one of said CJP processes has terminated its execution. 13. The combination as recited in claim 12 wherein said ready-queue is comprised of process links having a predetermined format each process link being associated with a predetermined one of said processes, said process links being arranged in said ready queue in accordance to a FIFO (first-in-first-out) priority. 14. The combination as recited in claim 13 including in each of said process links sixth means for storing signals of an address for said process associated with said process link. 15. The combination as recited in claim 14 including in each of said process link seventh means for storing signals of a priority number for said process associated with said process link. 16. The combination as recited in claim 15 including in each of said process links eighth means for storing signals of an address of the process link next in line in the queue of ready processes. 17. The combination as recited in claim 16 including ninth means in said first means for storing signals indicative of a priority number to its associated process (CJP) currently in control of said CPU for indicating priority for control of said CPU in relation to other processes in contention for said CPU. 18. The combination as recited in claim 17 including tenth means communicting with said first, second, third and fourth means for comparing the priority number of said running process (CJP) with the priority number of said first process (NJP) first in line for control of said CPU. 19. The combination as recited in claim 18 including in said first means eleventh means, responsive to a first signal from said control unit, for storing signals representing information in said general registers. 20. The combination as recited in claim 19 including in said first means, twelfth means responsive to a second signal from said control unit, for storing signals indicating information available to said base registers. 21. The combination as recited in claim 20 including in said first means, thirteenth means responsive to a third signal from said control unit, for storing signals indicating information available to said scientific registers. 22. The combination as recited in claim 21 including in said first means, fourteenth means responsive to a fourth signal from said control unit, for storing signals of information in said status register. 23. In a multiprogramming computer system comprising a main memory, a central processing unit (CPU) communicating with said main memory, said multiprogramming computer system including a plurality of processes stored in said main memory, and a plurality of queues also stored in said main memory, each of said plurality of processes having a predetermined priority number with respect to others of said processes and wherein a selected one of said processes (CJP) is running (i.e. in control of said CPU), with selected others of said plurality of processes being in a ready state (i.e. in condition to obtain control of said CPU), and with information relative to said processes in the ready state being stored in one of a plurality of said ready queues, each of said ready queues located at a starting location in said main memory designated as a ready queue head a process management unit for supervising the state of said processes comprising: (a) first means for queueing information relative to said ready processes into a ready-queue on the basis of a first-in-first-out (FIFO) arrangement, with the ready queue head of said ready queue identifying a first process (NJP) first in line for control of said CPU; (b) second means, communicating with said first means, for storing signals representing an address of the ready queue head of said ready-queue; (c) means responsive to said second means for addressing the head of said ready queue; (d) third means in said head of said ready-queue, for storing signals indicating a priority number of said first process (NJP) first in line for control of said CPU; (e) fourth means for storing signals indicating a priority number for said running process (CJP); and, (f) fifth means, communicating with said first, second, third and fourth means for comparing the signals indicative of the priority number of said running process (CJP) with the signals indicative of the priority number of said first process (NJP) first in line for control of said CPU. 24. The combination as recited in claim 23 including sixth means communicating with said fifth means, for providing signals for removing said running process (CJP) from control of said CPU, and seventh means communicating with said fifth means providing signals for installing said first process (NJP) in control of said CPU. 25. The combination as recited in claim 24 wherein said first process (NJP) is associated with a first process link at the head of said ready queue, and including eighth means for providing signals for removing said first process link from the head of said ready queue, after said first process (NJP) is installed in control of said CPU. 26. The combination as recited in claim 24 including a plurality of general registers in said CPU for temporarily storing information pertaining to the operation of said CPU and further including a plurality of process control blocks (PCB's) associated with said processes, one PCB being associated with one process and with said running process (CJP) being associated with a running PCB. 27. The combination as recited in claim 26 including a control unit in said CPU for providing signals for controlling said CPU and further including ninth means in said PCB responsive to a first signal from said control unit and communicating with said first, second, third, fourth and fifth means, for storing the contents of said general registers into said ninth means of said running PCB prior to the removal of said running process (CJP) from control of said CPU. 28. The combination as recited in claim 27 including a plurality of base registers in said CPU, for temporarily storing signals of information relating to the operation of said CPU and further including tenth means, in said PCB, responsive to a second signal from said control unit and communicating with said first, second, third, fourth and fifth means, for storing the contents of said base registers into said tenth means of said running PCB prior to the removal of said running process (CJP) from control of said CPU. 29. The combination as recited in claim 28 including a plurality of scientific registers in said CPU, for temporarily storing information relating to a scientific mode operation of said CPU and further including eleventh means in said PCB, responsive to a third signal from said control unit and communicating with said first, second, third, fourth and fifth means, for storing the contents of said scientific registers into said eleventh means of said running PCB prior to the removal of said running process from control of said CPU. 30. The combination as recited in claim 29 including a status register in said CPU for temporarily storing signals of information relating to the status of said CPU and further including twelfth means in said PCB, responsive to a fourth signal from said control unit and communicating with said first, second, third, fourth and fifth means for storing the contents of said status register into said twelfth means of said running PCB prior to the removal of said running process CJP from control of said CPU. 31. In a multi-programming computer system comprising at least one main memory for storing a plurality of processes and including a plurality of queues, and at least one central processing unit CPU for executing said plurality of processes said main memory communicating with said CPU and wherein a selected one of said processes is a running process (CJP) in control of said CPU, with a first group of selected others of said plurality of processes being in a ready state (i.e. in condition to obtain control of said CPU), and with information relative to said processes in the ready state being stored in a ready-queue of said plurality of queues, each of said queues located at a starting location in said main memory designated as a queue head, a second group of selected others of said plurality of processes being in a wait state (i.e. require a predetermined event to occur before being placed in a ready state), and with information relative to said processes in said wait state being stored in a wait queue of said plurality of queues each process of said first and second group of processes having assigned to it a predetermined priority number based on the relative importance to others of said processes a process management unit for supervising the state of said processes comprising: (a) first means for arranging said first group of processes into a ready-queue on a first-in-first-out basis (FIFO) said ready queue being in a first location in said main memory the start of which is designated as the ready queue head, with the ready queue head of said ready queue identifying a first process from said first group, first in line for control of said CPU; (b) second means for arranging said second group of processes into a wait-queue on a first-in-first-out basis (FIFO) said wait queue being in a second location in said main memory the start of which is designated as the wait queue head, on a first-in-first-out basis (FIFO); (c) a plurality of third means in said ready queue, communicating with said first means, one each of said third means associated with one each of said first group of processes, each of said third means for indicating a priority number for its associated process for control of said CPU; (d) a plurality of fourth means in said wait-queue, communicating with said second means, each of said fourth means associated with one each of said second group of processes, each of said fourth means for indicating a priority number for its associated process; and, (e) fifth means, communicating with said first, second, third and fourth means, for arranging the sequential execution of said first and second groups of processes in their respective queues in accordance with the priority numbers in said third and fourth means respectively and also in accordance to a first-in-first-out (FIFO) basis. 32. The computer system as recited in claim 31 wherein said ready queue is comprised of process links with the first link being the head of the ready queue, said computer system further including sixth means, communicating with said first and third means for addressing the head of said ready queue. 33. The computer system as recited in claim 32 including seventh means for indicating the priority number of said running process, and further including eighth means communicating with said third, fourth and seventh means for comparing with one another the priority numbers of said running process, of each of said first group of processes, and of each of said second group of processes. Other info: Inventors: Dufond, Patrick (Paris, FR) Cassonnet, Jean-Claude (Conflans-Ste-Honorine, FR) Bogaert, Jean-Louis (Clamart, FR) DE Rivet, Philippe-Hubert (Paris, FR) Bradley, John J. (Garches, FR) Franklin, Benjamin S. (Cambridge, MA, US) Application Number: 529012 Filing Date: 1974-12-02 Publication_date: 1978-04-11 Assignee: Compagnie Honeywell Bull (Paris, FR) Primary Class(es): 718/103 711/203, 718/107 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Nusbaum, Mark E. Assistant Examiner: Attorney: Prasinos; Nicholas, Reiling; Ronald T. |
|