Title: Bias control circuit for an audio amplifier utilizing an unsaturated junction type FET

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1. A bias control circuit for an audio amplifier utilizing an unsaturated junction type FET, the improvement wherein said amplifier includes at least an amplifier section formed of a complementary pair of one N channel and one P channel unsaturated junction type FETs constituting a single ended pushpull circuit, the N channel FET having a drain connected to the positive terminal of a first dc power source of a predetermined voltage and a source connected via a load to a ground potential, and the P channel FET having a drain connected to the negative terminal of the first dc power source and a source connected via the load to the ground potential; and wherein said bias control circuit comprises a first complementary pair of one PNP type-and one NPN type-bipolar transistors, the first PNP type bipolar transistor having a collector coupled to the gate of the N channel FET and connected via a first resistor to the negative terminal of a second dc power source with its voltage predetermined and fluctuated at substantially the same rate as that of the first dc power source and a base connected to the collector thereof via a second resistor, and the first NPN type bipolar transistor having a collector coupled to the gate of the P channel FET and connected via a third resistor of the same resistance value as the first resistor to the positive terminal of the second dc power source and a base connected to the collector thereof via a fourth resistor of the same resistance value as the second resistor, the bases of the bipolar transistors being also interconnected via a fifth common resistor and the emitters thereof being coupled in common to one terminal of an input audio signal source having the other terminal connected to the ground potential via sixth respective resistors of the same resistance value.

2. The bias control circuit claimed in claim 1, wherein the first dc power source across which the drains of the complementary pair of FET's are connected and the second dc power source across which the collectors of the complementary pair of bipolar transistors are coupled each comprise a full wave rectifier bridge having its input terminals connected to the both ends of a secondary power transformer winding which is electromagnetically coupled to a primary power transformer winding having its terminals connected across an ac power source.

3. The bias control circuit claimed in claim 1, wherein the fifth resistor interconnecting the bases of the complementary pair of bipolar transistors is of variable type.

4. The bias control circuit claimed in claim 1, wherein there is further provided, between the collectors of the complementary pair of bipolar transistors having their emitters coupled via the sixth respective resistors to the input audio signal source and the gates of the complementary pair of FET's, a driver circuit comprising a second complementary pair of one NPN type and one PNP type bipolar transistors constituting a single ended pushpull circuit, the second NPN type bipolar transistor having a base connected to the collector of the first NPN type bipolar transistor, a collector connected to the positive terminal of the second dc power source and an emitter connected to the gate of the P channel FET, and the second PNP type bipolar transistor having a base connected to the collector of the first PNP type bipolar transistor, a collector connected to the negative terminal of the second dc power source and an emitter connected to the gate of the N channel FET, the emitters of the second bipolar transistors being further interconnected via a common resistor.

5. The bias control circuit claimed in claim 4, wherein the first complementary pair of bipolar transistors have their emitters directly connected to the one terminal of the input audio signal source, with the other terminal connected to the ground potential.

6. The bias control circuit claimed in claim 1, wherein there are further provided, between the sixth respective resistors connected to the corresponding emitters of the first complementary pair of bipolar transistors and the one terminal of the input audio signal source with the other terminal connected to the ground potential, a driver circuit comprising a second complementary pair of one NPN type and one PNP type bipolar transistors constituting a single ended pushpull circuit, the second NPN type bipolar transistor having an emitter connected via the sixth corresponding resistor to the emitter of the first NPN type bipolar transistor and a collector connected to the positive terminal of the second dc power source, and the second PNP type bipolar transistor having an emitter connected via the sixth corresponding resistor to the emitter of the first PNP type bipolar transistor and a collector connected to the negative terminal of the second dc power source, the second bipolar transistors having their bases interconnected via a seventh common resistor; and a preamplifier circuit comprising a third complementary pair of one PNP type and one NPN type bipolar transistors, the third PNP type bipolar transistor having a collector connected to the base of the second NPN type bipolar transistor, an emitter connected via an eighth resistor to the positive terminal of the second dc power source and a base coupled to a constant base bias voltage source, and the third NPN type bipolar transistor having a collector connected to the base of the second NPN type bipolar transistor, an emitter connected via a ninth resistor to the negative terminal of the second dc power source and a base coupled to the one terminal of the input audio signal source with the other terminal connected to the ground potential, the collectors of the third complementary pair of bipolar transistors being further interconnected via a common load resistance network.

7. The bias control circuit claimed in claim 6, wherein the common load resistance network inter connecting the collectors of the third complementary pair of bipolar transistors comprises a fourth NPN type bipolar transistor constituting a constant current source and having a collector connected to the collector of the third PNP type bipolar transistor, an emitter connected via a tenth resistor to the collector of the third NPN type bipolar transistor, and a base connected to the collector thereof via an eleventh resistor and also to the collector of the third PNP type bipolar transistor via a twelfth resistor.

8. The bias control circuit claimed in claim 6, wherein the common load resistance network interconnecting the collectors of the third complementary pair of bipolar transistors comprises a single resistance element.

9. The bias control circuit claimed in claim 6, wherein the gates of the complementary pair of FET's are connected directly to the corresponding collectors of the first complementary pair of bipolar transistors.

Other info:

Inventors: Shizuhara, Shuji (Akikawa, JA)

Application Number: 643409
Filing Date: 1975-12-22
Publication_date: 1976-10-05
Assignee: Sansui Electric Co., Ltd. (Tokyo, JA)
Primary Class(es): 330/269 330/273
Other Classes:
US Patent Ref:

3921089

Nov, 1975

Tsurushima

330/35.

Other Refs:
Primary Examiner: Rolinec, R. V.
Assistant Examiner: Dahl, Lawrence J.
Attorney: Harris, Kern, Wallen & Tinsley