Title: Fail safe logic monitor

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Claims: What is claimed is:

1. A fail safe system for monitoring a multi-bit logic word, comprising:

first multiplexing means for multiplexing the multi-bit logic word;

second multiplexing means for multiplexing a multi-bit reference word;

first gating means connected to the first multiplexing means for gating the output therefrom;

second gating means connected to the second multiplexing means for gating the output therefrom;

comparator means connected to the first and second gating means and responsive to the gated outputs therefrom for providing an alternating output when the gated outputs are in substantial agreement, and otherwise providing a constant level output;

first means connected to the comparator and to the first multiplexing means and responsive to the alternating comparator output for providing an address for the first multiplexing means;

second means connected to the comparator and to the second multiplexing means and responsive to the alternating comparator output for providing an address for the second multiplexing means;

each of the first and second means including means connected to the comparator for dividing the frequency of the alternating output therefrom, counting means connected to the frequency dividing means and to a corresponding multiplexing means, and responsive to the divided comparator output for providing the address for said multiplexing means; and

the counting means in each of the first and second means being normally synchronized, with an internal system failure rendering the counters desynchronized, whereupon the gated outputs are otherwise than in substantial agreement and the comparator means provides the constant level output.

2. A system as described by claim 1, wherein:

the counting means is responsive to the constant level output from the comparator means to stop counting, and to thereby render the system in a latched condition which is indicative of a fault in the multi-bit logic word.

3. A system as described by claim 1, wherein each of the first and second means further includes:

means for resetting the frequency dividing means and the counting means.

4. A system as described by claim 1 including means for testing the second multiplexing means, said testing means including:

means for applying a test signal at a predetermined logic level to the first and second gating means;

the first gating means responsive to the test signal for blocking the output from the first multiplexing means; and

the second gating means including means responsive to the test signal for being set by the output of the second multiplexing means for testing said means.

5. A system as described by claim 1, wherein the frequency dividing means in each of the first and second means includes:

a flip-flop connected to the comparator means; and

a voltage limiting device connected intermediate the comparator and the flip-flop.

6. A system as described by claim 1, wherein each of the first and second multiplexing means includes:

a first multiplexer for multiplexing a portion of the bits of the word multiplexed by the multiplexing means; and

a second multiplexer for multiplexing the remaining bits of said word.

Other info:

Inventors: Rock, Michael H. (Glen Rock, NJ, US)

Application Number: 559346
Filing Date: 1975-03-17
Publication_date: 1976-09-28
Assignee: The Bendix Corporation (Teterboro, NJ)
Primary Class(es): 714/761 340/146.2
Other Classes:
US Patent Ref:

3688099	Aug, 1972	Buscher	244/77.
3784980	Jan, 1974	Geesen	340/146.
3892923	Jul, 1975	Ranner	179/15.

Other Refs:
Primary Examiner: Robinson, Thomas A.
Assistant Examiner:
Attorney: Cuoco; Anthony F.