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Title: Digital data communications system packet switch



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Claims: I claim:

1. In a data communication system, a packet switch for routing a packet of data through said communications system, said packet switch including a packet store having a plurality of queues for storing respective packets of data, and characterized in that said packet switch comprises:

an input terminal adapted for receiving an input frame of data, said input frame including a first plurality of time slots, an input frame time slot having a packet of data;

an output terminal adapted for transmitting an output frame of data, said output frame including a second plurality of time slots, an output frame time slot for inserting a packet of data;

means including a control memory for extending a packet received at said input terminal through said packet store to said output terminal;

said control memory including means for controlling the transfer of a packet from a first time slot of said input frame to a second time slot of said output frame, each time slot having a predetermined identification and each packet having a header for routing said transfer;

said transfer controlling means responsive to said first time slot identification and said header of said packet including first means for providing a second packet header for said packet and second means for providing an output signal corresponding to said second time slot identification.

2. The packet switch according to claim 1 further comprising:

means including a queue control for replacing said first packet header with said second packet header.

3. The packet switch according to claim 2 wherein said queue control comprises:

means, responsive to said output signal of said second providing means, for storing said packet of data including said second packet header in a packet store queue corresponding to said output signal.

4. The packet switch according to claim 3 wherein said queue control storing means comprises:

first queue position means individual to a queue for determining a first memory cell in said queue into which said packet of data is to be stored.

5. The packet switch according to claim 3 wherein said queue control storing means comprises:

second queue position means individual to a queue for determining a second memory cell in said queue from which a second packet of data is to be read.

6. The packet switch according to claim 5 wherein said queue control further comprises:

means, responsive to said output signal of said second providing means, for inserting said second packet including said second packet header in said second time slot.

7. The packet switch according to claim 4 wherein said queue control storing means further comprises:

second queue position means individual to said queue for determining a second memory cell in said queue from which a second packet of data is to be read.

8. The packet switch according to claim 7 wherein said queue control further comprises:

means, responsive to said first and second queue position means, for comparing a first and a second memory cell address, said first and said second memory cell addresses corresponding respectively to said first and said second memory cells; and

means responsive to said comparing means for providing a queue empty signal if said first and said second memory cell addresses are equal.

9. The packet switch according to claim 8 wherein said queue control further comprises:

means, responsive to said queue empty signal, for providing a predetermined fill packet.

10. The packet switch according to claim 9 wherein said queue control further comprises:

means, responsive to said second providing means, for inserting said predetermined fill packet in said second time slot.

11. The packet switch according to claim 7 wherein said queue control further comprises:

means, responsive to said first and second queue position means, for comparing a first and a second memory cell address, said first and said second memory cell addresses corresponding to respectively said first and said second memory cells; and

means, responsive to said comparing means, for providing a queue full signal if said first and said second memory cell addresses differ in a predetermined manner.

12. The packet switch according to claim 11 wherein said queue control further comprises:

means, responsive to said queue full signal, for rejecting said packet of data.

13. In a digital data communications system, a packet switch for routing a packet of data through said communications system, said packet of data including a packet header, said packet switch comprising:

a packet store having a plurality of memory cells, each memory cell for storing a packet of data;

means including a control memory and a queue control for extending said packet of data to be routed from an input terminal through said packet store to an output terminal:

said control memory for controlling the transfer of said packet from a first time slot in an input frame provided to said input terminal to a second time slot in an output frame provided to said output terminal, each time slot having a predetermined identification, said control memory including means responsive to said packet header of said packet for providing a second packet header; and

said queue control for transferring said packet from said first time slot through a memory cell in said packet store to said second time slot, said queue control including means for replacing said packet header with said second packet header.

14. The packet switch according to claim 13 wherein said queue control further comprises:

a pointer store having a plurality of queues for storing a pointer to a memory cell in said packet store;

means for identifying an empty state of a memory cell; and

means responsive to said second time slot identification for providing said pointer to said memory cell through said identifying means to a respective one of said queues in said pointer store.

Other info:


Inventors: Fraser, Alexander Gibson (Bernardsville, NJ, US)

Application Number: 575937
Filing Date: 1975-05-09
Publication_date: 1976-09-07
Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ)
Primary Class(es): 710/316 370/395.71, 370/412, 370/422
Other Classes:
US Patent Ref:
3883855May, 1975Brightman et al.340/172.
3891807Jun, 1975Charransol et al.179/15.
3906161Sep, 1975Schlichte179/15.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Bartz, C. T.
Attorney: Roddy; Richard J.