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Title: Method and device for driving in time division fashion field effect mode liquid crystal display device for numeric display



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Claims: I claim:

1. A method of driving in time division fashion a field effect mode liquid crystal display device for numeric display, having a plurality of sets of segment electrodes, each set being provided for one digit, and a plurality of separated digit electrodes disposed opposite to the plurality of segment electrode sets respectively, the corresponding segment electrodes of the respective digits being commonly interconnected, said method comprising the steps of maintaining the amplitude of a.c. voltages applied to the display points in the half-selected and the non-selected states when the associated digit electrodes are not selected at a constant value, while controlling the effective value of a.c. voltages applied to the display points in the selected states by changing the duty ratio of the width of the selection pulse to the time interval of the successive selection pulses.

2. A method according to claim 1, wherein the highest voltage V.sub.0 applied to said segment and digit electrodes is divided into three voltage levels V.sub.0, V.sub.1 and V.sub.2 (V.sub.0 >V.sub.1 >V.sub.2 >0), and the divided voltages are suitably combined to apply a desired display point a voltage of .+-. V.sub.0 in the selected state and a voltage of about .+-. 1/3 V.sub.0 in the half-selected state and the non-selected state.

3. A method according to claim 1, wherein the step of changing the duty ratio changes the color of the display points in the selected state.

4. A device for driving in time division fashion a field effect mode liquid crystal display device for numeric display, having a plurality of sets of segment electrodes, each set being provided for one digit, and a plurality of separated digit electrodes disposed opposite to the plurality of segment electrode sets respectively, the corresponding segment electrodes of the respective digits being commonly interconnected, said device comprising a digit drive array for driving the respective digit electrodes, a digit scanner for scanning said digit drive array, a segment drive array for driving the respective segment electrodes, and a character generator for supplying a character signal to said segment drive array, the improvement comprising further a duty ratio selection circuit, whereby said digit scanner is controlled by the output of said duty ratio selection circuit to render the duty ratio variable.

5. A device according to claim 4, wherein the duty ratio selection circuit includes a plurality of AND gates each providing an output to an OR gate, the output of the OR gate determining the ratio for the digit scanner.

6. A device according to claim 5, further comprising a color selection circuit and a frequency selection circuit, each of the AND gates of the duty ratio selection circuit receiving at least one input from the color selection circuit and the frequency selection circuit.

7. A device according to claim 6, further comprising first clock generator means for supplying a first clock signal to the segment drive array and an inverted first clock signal to the digit drive array, and a second clock generator means for supplying a second clock signal to the frequency selection circuit, the digit scanner and the character generator, the second clock generator means being synchronized with the first clock generator means.

8. A device according to claim 7, wherein the first clock generator means provides a first clock signal having an output frequency of 2f and the second clock generator means is responsive to the first clock generator means for providing an output having a frequency f.

Other info:


Inventors: Kawakami, Hideaki (Hitachi, JA)

Application Number: 471602
Filing Date: 1974-05-20
Publication_date: 1976-08-17
Assignee: Hitachi, Ltd. (JA)
Primary Class(es): 345/52 345/88, 349/142
Other Classes:
US Patent Ref:
3711180Jan, 1973Klinger et al.358/61.
3758195Sep, 1973Hedman et al.350/160.
3835463Sep, 1974Tsukamoto et al.340/324.

Other Refs:
Primary Examiner: Trafton, David L.
Assistant Examiner:
Attorney: Craig & Antonelli