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Title: Control arrangement fail-safe timing circuit
Claims: I claim: 1. In a control arrangement for activating a system, a fail-safe timing circuit energizable in response to a request signal, said fail-safe timing circuit comprising first switching means operable when enabled to activate the system to commence its operation tentatively, second switching means operable when enabled to enable said first switching means, first timing means including first charge retaining means responsive to said request signal for charging toward a given potential to provide an increasing potential at a first control input of said second switching means, and second charge retaining means responsive to said request signal for discharging from said given potential to provide a decreasing potential at a second control input of said second switching means, said second switching means being enabled when the potential at said second control input decreases to a value which is a predetermined amount less than the potential at said first control input to enable said first switching means, second timing means responsive to said request signal for generating a time-out signal after a predetermined time delay interval for inhibiting said first timing means whereby said first and second switching means are disabled to de-activate the system, and circuit means responsive to a system variable becoming a predetermined condition for preventing said second timing means from generating its time-out signal. 2. A fail-safe timing circuit according to claim 1, further including discharge circuit means for resetting said second timing means responsive to the absence of said request signal. 3. A fail-safe timing circuit according to claim 2, wherein said second timing means includes a capacitor and a capacitor-charging resistance means, said discharge circuit means including a discharge resistance path coupled to said capacitor. 4. In a control arrangement for activating a system, a fail-safe timing circuit energizable in response to a request signal, said fail-safe timing circuit comprising first switching means operable when enabled to activate the system to commence its operation tentatively, second switching means operable when enabled to enable said first switching means, first charge retaining means responsive to said request signal for charging toward a given potential to provide an increasing potential at a first control input of said second switching means, second charge retaining means responsive to said request signal for discharging from said given potential to provide a decreasing potential at a second control input of said second switching means, said second switching means being enabled when the potential at said second control input decreases to a value which is a predetermined amount less than the potential at said first control input to enable said first switching means, third charge retaining means responsive to said request signal for charging toward said given potential for controlling the discharging of said third charge retaining means to prevent the potential at said second control input from reaching said predetermined value to thereby cause said second switching means to disable said first switching means to de-activate the system, and variable sensing means responsive to a system variable assuming a predetermined condition for preventing said third charge retaining means from causing the system from becoming deactivated. 5. A fail-safe timing circuit according to claim 4, wherein said second switching means includes pulse means for producing a series of pulses to cause said first switching means to become operative during each pulse and for permitting said first switching means to become inoperative alternately in the absence of said pulses, said pulse means including delay means for maintaining the system operative for a predetermined time delay interval, said interval being substantially greater than the interval of time between said pulses. 6. A fail-safe timing circuit according to claim 5, wherein said pulse means includes a rectifying means for converting alternating current signals to half wave rectified signals for producing said pulses. 7. A fail-safe timing circuit according to claim 6, wherein said first switching means includes a first bi-stable device for controlling said system and a second bi-stable device for controlling said first bi-stable device in response to said pulses. 8. A fail-safe timing circuit according to claim 7, wherein said first bi-stable device comprises a relay. 9. A fail-safe timing circuit according to claim 7, wherein said second bi-stable device comprises a silicon controlled rectifier. 10. In a control arrangement for activating a system, a fail-safe timing circuit energizable in response to a request signal, said fail-safe timing circuit comprising switching means operable when enabled to activate the system to commence its operation, a controlled switching device operable when enabled for enabling said switching means, first timing means including a first capacitor means responsive to said request signal for charging toward a given potential to provide an increasing potential at a first control input of said controlled switching device, and a second capacitor means responsive to said request signal for discharging from said given potential to provide a decreasing potential at a second control input of said controlled switching device, said controlled switching device being enabled when the potential at said second control input decreases to a value which is a predetermined amount less than the potential at said first control electrode to enable said switching means, second timing means for inhibiting said first timing means after a predetermined time interval following the occurrence of said request signal to cause said controlled switching device to disable said switching means to de-activate the system, and circuit means responsive to a system variable becoming a predetermined condition for preventing said second timing means from inhibiting said first timing means. 11. In a control arrangement for activating a system, a fail-safe timing circuit energizable in response to a request signal, said fail-safe timing circuit comprising switching means operable when enabled to activate the system to commence its operation, a controlled switching device having a first control input, a second control input, and an output connected to an enabling input for said switching means, first capacitor means connected to said first control input and responsive to said request signal for charging toward a given potential to provide an increasing potential at said first control input, second capacitor means connected to said second control input and responsive to said request signal for discharging from said given potential to provide a decreasing potential at said second control input, said controlled switching device being enabled when the potential at said second control input decreases to a value which is a predetermined amount less than the potential at said first control input to enable said switching means to activate the system, third capacitor means responsive to said request signal for charging toward said given potential for controlling the discharging of said second capacitor means to prevent the potential at said second control input from reaching said predetermined value to thereby cause said controlled switching device to disable said switching means to de-activate the system, and sensing means responsive to a system variable assuming a predetermined condition for preventing said third capacitor means from causing the system to be deactivated. Other info: Inventors: Matthews, Russell B. (Goshen, IN, US) Application Number: 447165 Filing Date: 1974-03-01 Publication_date: 1976-07-20 Assignee: Johnson Service Company (Milwaukee, WI) Primary Class(es): 307/141 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Smith, Jr., David Assistant Examiner: Attorney: Johnson, Dienner, Emrich & Wagner |
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