Title: Memory operation for 3-way communications

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Claims: What is claimed is:

1. Memory means for use in a time division multiplex telephone switching system employing pulse code modulation, wherein said switching system operates under control of a connected central processor unit which generates control signals in accordance with an internal program and external call requests from a plurality of subscribers, said memory means comprising: a sequence generator including an input circuit connection to said central processor unit and a plurality of output connections, operating in response to cyclically recurring signals received from said central processor unit to generate a plurality of control signals; a control memory comprising first and second memory portions, each including circuit connections to said central processor unit and to said sequence generator; control memory multiplex means including first and second portions connected between said central processor unit and said control memory and including circuit connections to said sequence generator, operated in response to control signals from said sequence generator to selectively couple address information from said central processor unit to one of said control memory portions for storage therein; an information memory comprising first and second pairs of memory portions and including circuit connections to said switching system and to said sequence generator; information memory multiplex means comprising first and second pairs of multiplex portions and including circuit connections to said sequence generator; said first pair of multiplex portions connected between said first control memory portion and said first pair of information memory portions and said second multiplex portion pair connected between said second control memory portion and said second pair of information memory portions; said information memory multiplex means operated in response to cyclic signals from said sequence generator to couple information stored in said control memory portions to said information memory portions; and output control means including an output connection to said telephone switching system and circuit connections to said sequence generator and said information memory; said information memory operated in response to control information from said control memory coupled through said information address multiplexer, to store pulse code modulated data from said switching system, and in response to said sequence generator signals couple said coded data to said output control means; said control means periodically operated in response to said sequence generator to couple said data from said output control means to said telephone switching system.

2. Memory means as claimed in claim 1 wherein said sequence generator includes: counting means including an input circuit connected to said central processor unit and output circuit connections to said control memory multiplex means and to said information memory multiplex means, operated in response to said cyclically recurring pulses to provide operating signals to both of said multiplex means.

3. Memory means as claimed in claim 2 wherein said sequence generator further includes: a flip-flop circuit including an input circuit connected to said counting means and a first output circuit connected to a first portion of each pair of information memory multiplex means portions and connected to a first portion of each pair of information memory means portions, and a second output circuit connected to a second portion of each pair of information memory multiplex means portions and connected to a second portion of each pair of information memory means portions, said flip-flop periodically operated to provide output signals alternately on said first and second output circuits for conduction to said connected information memory multiplex means and said connected information memory means.

4. Memory means as claimed in claim 2 wherein said sequence generator further includes: a control pulse generator including an input circuit connected to said central processor unit and a first output circuit connected to both of said multiplex means and second and third output circuits connected to said output control means.

5. Memory means as claimed in claim 1 wherein said output control means include: comparator means; first and second storage means, each connected to a different one of said information memory portion pairs and each connected to said comparator means, operated in response to periodic control pulses from said sequence generator to store pulse code modulated data from said connected information memory means.

6. Memory means as claimed in claim 5 wherein said output control means further include: output selection means connected to said first and second storage means and to said comparator means, and an output circuit connected to said switching system; said comparator means operated in response to the magnitude of the data stored in one of said storage means being higher than that stored in the other said storage means, to generate a control signal to said output selection means, said output selection means operated in response to said control signal from said comparator means and a control signal from said sequence generator, to couple said higher magnitude pulse code modulated data to said switching system.

Other info:

Inventors: Srivastava, Dinesh K. (Westmont, IL, US)
Lee, David Q. (Chicago, IL, US)

Application Number: 606698
Filing Date: 1975-08-21
Publication_date: 1976-06-29
Assignee: GTE Automatic Electric Laboratories Incorporated (Northlake, IL)
Primary Class(es): 370/263 370/378
Other Classes:
US Patent Ref:

3046348	Jul, 1962	Osborn	179/15.
3632883	Jan, 1972	Aagaard	179/15.
3740482	Jun, 1973	Plank et al.	179/15.
3832492	Aug, 1974	Charransol et al.	179/15.
3927267	Dec, 1975	Voyer et al.	179/15.

Other Refs:
Primary Examiner: Robinson, Thomas A.
Assistant Examiner:
Attorney: Black; Robert J.