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Title: Fire-alarm audible signaling system permitting selective communications and signaling
Claims: I claim: 1. A fire-alarm audible signaling system permitting selective communications and signaling and comprising transmitter means, receiver-driver means, and circuit means connecting said transmitter means and said receiver-driver means, wherein said transmitter means comprises logic means for generating information in digital form, a ones oscillator for continuously generating a tone of a first frequency representing digital ones, a zeros oscillator for continuously generating a tone of a second frequency representing digital zeros, a pair of field-effect transistor switch means electrically connected between said circuit means and said oscillators, respectively, and a pair of NAND-gates having outputs respectively connected to gate said field-effect transistor switch means, whereby said respective field-effect transistor switch means open and close in accordance with said digital information generated by said logic means in order to impress on said circuit means a series of tone bursts of different frequencies conveying said information. 2. A system according to claim 1 wherein said circuit means consists of two wires which carry both power and the digital information. 3. A system according to claim 1 wherein said circuit means consists of three wires which serve, respectively, as a power line, a data line, and a common ground. 4. A fire-alarm audible signaling system permitting selective communications and signaling and comprising transmitter means, receiver-driver means, and circuit means connecting said transmitter means and said receiver-driver means, wherein said transmitter means comprises logic means for generating information in digital form, a ones oscillator for continuously generating a tone of a first frequency representing digital ones, a zeros oscillator for continuously generating a tone of a second frequency representing digital zeros, and a pair of switch means electrically connected between said circuit means and said oscillators, respectively, said respective switch means opening and closing in accordance with said digital information generated by said logic means in order to impress on said circuit means a series of tone bursts of different frequencies conveying said information, said logic means comprising memory means for storing a plurality of multi-bit digital words each comprising a zone designator and a function designator, said memory means having multiple output leads, means for sequentially selecting and reading out said words to present the bits constituting the selected word in parallel format on said output leads, readout multiplexer means connected to said output leads and to said switch means, and binary-counter means connected to said readout multiplexer means for causing said readout multiplexer means to sample said output leads sequentially, whereby the digital bits constituting the selected word are effective sequentially to control the opening and closing of said switch means. 5. A system according to claim 4 wherein the means for sequentially selecting and reading out said words comprises additional binary-counter means connected to said memory means and first clock means for producing clock pulses for indexing said additional binary-counter means. 6. A system according to claim 5 further comprising transmitter input multiplexer means and a plurality of data input leads to said transmitter input multiplexer means, each of said data input leads being capable of carrying a signal representing a designated function to be performed in a designated zone, said additional binary counter means also supplying a count to said transmitter input multiplexer means and said clock pulses also strobing said transmitter input multiplexer means, whereby said data input leads to said transmitter input multiplexer means are sampled sequentially, said transmitter input multiplexer means producing an output in dependence on the signal on the data input lead being sampled, and said output of said transmitter input multiplexer means facilitating control of the operation of said first clock means. 7. A system according to claim 4 comprising second clock means for producing additional clock pulses for indexing said binary counter means, further comprising means for accumulating said pulses and producing an output upon accumulation of a predetermined number of said pulses effecting an interruption of the transmission of information from said transmitter means to said receiver-driver means. 8. A system according to claim 7 wherein said receiver-driver means comprises means for providing to said transmitter means during said interruption an indication of whether or not said receiver-driver means is in working order. 9. A system according to claim 3 wherein said transmitter means further comprises a plurality of signal-generating means, a corresponding plurality of modulator means respectively modulating the signals generated by said signal-generator means, and a corresponding plurality of switch means for selectively transmitting the signals as modulated to said circuit means, said plurality of switch means being controlled in accordance with selected ones of the bits represented by the tone bursts impressed on said circuit means. 10. A system according to claim 9 wherein said receiver-driver means comprises a corresponding plurality of demodulator means controlled in accordance with the same selected bits. Other info: Inventors: Antonaccio, Joseph C. (Hazlet, NJ, US) Application Number: 480867 Filing Date: 1974-06-19 Publication_date: 1976-06-15 Assignee: Wheelock Signals, Inc. (Long Branch, NJ) Primary Class(es): 340/310.01 340/328, 340/538, 340/825.76 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Pitts, Harold I. Assistant Examiner: Attorney: Brumbaugh, Graves, Donohue & Raymond |
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