Title: Computer control apparatus

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1. Control apparatus for a stored program computer having an instruction cycle, said instruction cycle including an instruction fetch cycle, said instruction fetch cycle taking a finite period of time, said finite period of time including a portion of time for forming an address for the next instruction to be fetched, followed by an instruction execution cycle, said instruction execution cycle taking a finite period of time at least equal to said portion of time for forming an address for the next instruction to be fetched the improvement comprising

means for fetching and executing instructions, decoding means connected to said means for fetching and executing instructions for identifying that the instruction fetched is a branch instruction;

means connected to said means for fetching and executing instructions for forming the "branch to" instruction address during the execution of an instruction identified by said decoding means as a branch instruction and for furnishing said "branch to" instruction address to said means for fetching and executing instructions to enable the same to fetch said "branch to" instruction, and

means responsive to said decoding means identifying the instruction fetched as a branch instruction for generating a control signal for skipping said portion of time for forming an address for the next instruction to be fetched during said instruction fetch cycle for said "branch to" instruction and furnishing said control signal to said means for fetching and executing instructions.

2. Control apparatus for a stored program computer having an instruction fetch cycle taking a finite period of time, said finite period of time including a portion of time for setting an address for the next instruction to be fetched, followed by an instruction execution cycle taking finite period of time at least equal to said portion of time for setting an address for the next instruction to be fetched and including storage means for storing instructions at addressable storage positions, storage addressing means connected to said storage means and selectively loadable with addresses for indicating storage positions at which data is to be stored or retrieved, address register means for receiving addresses for the next instruction to be fetched and providing said addresses to said storage addressing means, selectively operable means for transferring addresses from said address register means to said storage addressing means, instruction register means for receiving instructions retrieved from storage, timing means for providing a plurality of successive timing signals for controlling said instruction fetch and execution cycles by controlling the loading of said storage addressing means at a first time during said instruction fetch cycle and at a fourth time during said instruction execution cycle and controlling the loading of said instruction register means at a third time during said instruction fetch cycle, instruction decode means operative to decode instructions in said instruction register means to provide signals indicating the type of instruction, the improvement comprising:

address forming means responsive to said instruction decode means providing a signal indicating a branch instruction for forming an address for a "branch to" instruction,

means for loading said address formed by said address forming means into said storage addressing means during said fourth time, and

timing control means responsive to said signal indicating a branch instruction for causing said timing means to skip said first time of the instruction fetch cycle of said "branch to" instruction by advancing directly from said fourth time of said instruction execution cycle of the branch instruction to a second time of the instruction fetch cycle of said "branch to" instruction.

3. The control apparatus of claim 2 wherein said address forming means includes

means for combining data from said address register with data from said branch instruction to form a "branch to" address.

4. The control apparatus of claim 3 wherein said combining means comprises AND circuitry gated by a signal occurring at said fourth time and said signal indicating a branch instruction and connected to pass predetermined bits from said address register with predetermined bits from said branch instruction to said storage addressing means upon being gated.

5. The control apparatus of claim 2 wherein said means for loading said address formed by said address forming means into said storage addressing means during said fourth time comprises logic circuitry gated by a signal occurring at said fourth time and connected to pass a signal to said storage addressing means.

6. The control apparatus of claim 2 wherein said timing control means comprises first logic circuitry gated by said signals indicating a branch instruction and said fourth time to generate an advance time signal, and

second logic circuitry responsive to said advance time signal for switching said timing means into said second time immediately upon the termination of said fourth time.

7. Control apparatus for a stored program computer having an instruction fetch cycle followed by an instruction execution cycle and including storage means for storing instructions at addressable storage positions, storage addressing means connected to said storage means and selectively loadable with addresses for indicating storage positions at which data is to be stored or retrieved, address register means for providing addresses to said storage addressing means, selectively operable means for transferring addresses from said address register means to said storage addressing means instruction register means for receiving instructions retrieved from storage, timing means for providing a plurality of successive timing signals for controlling said instruction fetch and execution cycles by controlling the loading of said storage addressing means at a first time during said instruction fetch cycle and at a fourth time during said instruction execution cycle and controlling the loading of said instruction register means at a third time during said instruction fetch cycle, instruction decode means operative to decode instructions in said instruction registers, means to provide signals indicating the type of instruction, branch condition logic means responsive to said instruction decode means providing a signal indicating a branch on condition instruction for generating a signal indicating that the branch condition is met, the improvement comprising

address forming means responsive to said instruction decode means providing a signal indicating a branch on condition instruction and responsive to said branch condition logic means providing a signal indicating that the branch condition is met for forming an address for a "branch to" instruction,

means for loading said address formed by said address forming means into said addressing means during said fourth time, and

timing control means responsive to said signal indicating a branch on condition instruction for causing said timing means to skip said first time on the instruction fetch cycle of the following instruction by advancing directly from said fourth time of said instruction execution cycle of the branch on condition instruction to a second time of the instruction fetch cycle of the following instruction.

8. Control apparatus for a stored program computer having storage means for storing instructions at addressable locations, selectively loadable storage addressing means connected for addressing said storage means, address register means for containing storage addresses, selectively operable address transfer means connected for transferring storage addresses from said address register means to said storage addressing means, a selectively loadable instruction register connected to receive instructions from said storage means, timing means for providing a plurality of sequentially occurring discretely identified timing signals, means responsive to timing signals identified as first and fourth timing signals for generating load signals for loading said storage addressing means, means responsive to timing signals identified as second timing signals for accessing said storage means to make instructions at the addressed location available therefrom, means responsive to timing signals identified as third timing signals for generating load signals for loading said instruction register with instructions from said storage means, instruction decode means connected to said instruction register and to said timing means for generating signals indicating the type of instruction contained in said instruction register, the improvement comprising:

address transfer control means responsive to said timing signal identified as a first timing signal for operating said selectively operable address transfer means connected for transferring storage addresses from said address register means to said storage addressing means,

branch address forming means responsive to said instruction decode means providing a signal indicating a branch instruction for forming an address for a "branch to" instruction,

means for transferring said "branch to" instruction address to said storage addressing means for loading therein by said load signal generated in response to said fourth timing signal, and

timing control means responsive to said signal indicating a branch instruction for causing said timing means to skip said first timing signal whereby the next sequentially occurring timing signal is a second timing signal so that said address transfer control means is unable to operate said selectively operable address transfer means and the "branch to" address loaded into said storage addressing means addresses said storage means.

Other info:

Inventors: Bodner, Ronald E. (Rochester, MN, US)
Crooks, Thomas L. (Rochester, MN, US)
Magrisso, Israel B. (Coral Springs, FL, US)
Slack, Keith M. (Rochester, MN, US)
Smith, Richard S. (Boca Raton, FL, US)

Application Number: 529677
Filing Date: 1974-12-04
Publication_date: 1976-06-01
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Class(es): 712/234 711/213
Other Classes:
US Patent Ref:

3417379	Dec, 1968	Heard et al.	340/172.
3656123	Apr, 1972	Carnevale et al.	340/172.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Bartz, C. T.
Attorney: Voss; Donald F.