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Title: Highly available computer system
Claims: What is claimed is: 1. In a modular computer system including a plurality of individual processors, each having essentially the same structure and functional characteristics but capable of operating under different control programs, wherein each processor has its own instruction processing means, an arithmetic logic unit, storage means, and necessary address and data 1/0 registers the improvement which comprises error detecting means for indicating that any processor has a hard failure and means for transmitting a failure signal to a control means, bussing means including gating operable under control of said control means for selectively interconnecting the address and data registers of the storage means of each processor so that any processor may be functionally substituted for the storage means of its own or any other processor in the system; control means operative in response to a failure indicating signal from said error detection means to stop operation of the defective processor, interrupt the operation of a predetermined one of the non-defective processors and reconfigure said bussing means to connect the storage means of the defective processor to said predetermined non-defective processor and concurrently disconnect the storage means of the predetermined nondefective processor from said processor. 2. A modular computer system as set forth in claim 1, including means for continually updating the status data for tasks in process in each processor and means for transferring said status data from the storage means of said defective processor to said predetermined non-defective processor, whereby the task being performed by the defective processor can be picked-up by the non-defective processor at substantially the point at which the failure occurred. 3. A modular computing system as set forth in claim 2, wherein a fixed number of cycles are assigned to the nondefective processor for processing its own tasks and those of the other processor, and means for alternately connecting the defective processor's storage and the non-defective processor's storage to the non-defective processor. 4. A modular computing system as set forth in claim 3, including instruction counting means in said control means for determining a predetermined number of processing cycles, wherein the number of instructions executed are counted and compared with said predetermined number, means responsive to said counting means for switching storage after the predetermined number has been reached, means for resetting the instruction counter to 0 and for subsequently requesting it to count the instructions executed by the processor on the other task. 5. A modular computing system as set forth in claim 1, wherein said selectively operable bussing means includes individual address and data buses connecting the address and data registers of all the processors of the system to said busses through controllable gate circuits which are actuated by said control unit, the principal inputs to said control unit being "defective processor" information received from said error detection circuitry and "available processor" information indicating a processor which has the lowest task queue. 6. A modular computing system as set forth in claim 5, wherein said control unit includes a central processor, and two control registers for accommodating a control word, logic circuits connected to said control registers selectively actuable in accordance with the bit settings of said control word said logic circuits being operable to control the buss gating circuits to connect a given processor store to a selected processor over said bussing means and for selectively disconnecting a predetermined store from said bussing means. 7. A modular computing system as set forth in claim 6, wherein said control unit further includes a loadable counter and means for monitoring the contents thereof to control the distribution of work cycles of the non-defective processor during the processing of the tasks of both the non-defective and defective processor. Other info: Inventors: Blum, Arnold (Pforzheim, DT) Irro, Fritz (Boeblingen, DT) Sonntag, Guenther (Boeblingen, DT) Application Number: 547672 Filing Date: 1975-02-06 Publication_date: 1976-05-25 Assignee: International Business Machines Corporation (Armonk, NY) Primary Class(es): 714/11 Other Classes: US Patent Ref:
Other Refs: Other References: Chao, The System Organization of MOBIDIC B, 1959, Proc. of the Eastern Joint Computer Conference, pp. 101-107. | |