Title: Dual density 800 bpi NRZI and 1600 bpi PE read circuit for a digital magnetic tape transport

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Claims: What is claimed is:

1. A read circuit for a digital tape transport comprising:

a differentiator connected to receive a read head signal and generate a differentiated read head signal as an output;

an integrator circuit which is biased toward a predetermined no signal condition, the integrator circuit being connected to integrate the differentiated read head signal and generate an integrated differentiated read head signal as out output;

a latch connected to generate a latched first output signal when a transition occurs in the differentiated output signal while the integrated differentiated read head signal exceeds a selected threshold magnitude with respect to the no signal condition;

a gating circuit coupled to pass the differentiated read head signal as a second output signal when enabled; and

an envelope detector coupled to enable the gating circuit when the time between successive read head pulses of predetermined minimum magnitudes does not exceed a selected minimum time.

2. The read circuit according to claim 1 above, wherein the output of the integrator circuit is biased toward a first digital logic voltage level and moves toward a second digital logic voltage level when the differentiated read head signal indicates the leading edge of a logic "1" NRZI data signal.

3. The read circuit according to claim 2 above, wherein the latch is a flip-flop having a data input responsive to the output of the integrator and a clock input responsive to a transition of the differentiated read head signal.

4. The read circuit according to claim 3 above, further comprising a squaring circuit coupled between the differentiator and the integrator to drive the integrator with a squared differentiated signal.

5. The read circuit according to claim 4 above, further comprising an inverter circuit coupled to selectively invert the squared differentiated signal to always drive the integrating circuit with the same polarity signal at the leading edge of a logic "1" NRZI data signal and an opposite polarity signal at the trailing edge of a logic "1" NRZI data signal.

6. The read circuit according to claim 5 above, wherein the integrator circuit integrates the selectively inverted differentiated output of the inverter at the leading edge of a logic "1" NRZI data signal to drive the input of the flip-flop with a logic "1" data level at the time a transition occurs in the differentiated read head signal to clock the flip-flop.

7. The read circuit according to claim 5 above, wherein the inverter circuit includes a bipolar level detector circuit, a toggle flip-flop which is connected to successively toggle in the absence of an output from the level detector circuit and an EXCLUSIVE-OR gate having one input responsive to the squared differentiated read head signal, a second input responsive to an output of the toggle flip-flop and an output coupled to drive the integrator circuit, the level detector being coupled to generate an output when the read head signal exceeds first or second magnitudes with first or second polarities while the level detector is enabled by first or second output signals of the toggling flip-flop respectively.

8. The read circuit according to claim 5 above, further comprising a filter circuit coupled in series between the squaring circuit and the integrating circuit, the filter circuit having an output which changes in response to an input with a predetermined minimum time between successive changes in the output, and wherein the toggle flip-flop is connected to toggle sufficiently fast that more than two changes must occur in the output of the toggle flip-flop for every change in the output of the filter circuit.

9. The read circuit according to claim 1, further comprising a gate coupled to selectively pass the differentiated read head signal as output data only when enabled by a phase encode read enable signal which indicates that information is to be read from magnetic tape in a phase encoded format.

10. The read circuit according to claim 9 above, further comprising an envelope detector coupled to inhibit the differentiated read head signal in the absence of the reading of information having the same general frequency and magnitude as phase encoded data.

11. The read circuit according to claim 5 above, wherein the inverter circuit includes a pair of opposite polarity level detector circuits which are separately enableable, each being connected to generate an output when the read head signal exceeds a selected clipping level while enabled, the two outputs being logically ORed, and a toggling flip-flop connected to toggle in the absence of an output from the level detector circuits and to cease toggling in response to an output from the level detector circuits, the toggling flip-flop having one output coupled to enable one inverter circuit and an inverted output opposite the one output coupled to enable the other level detector, the toggling flip-flop being further coupled to activate both outputs in response to a phase encode signal indicating that information is to be read from magnetic tape.

12. The read circuit according to claim 11 above, further comprising a first output gating circuit coupled to pass the latched output signal only in response to an NRZI signal and a second gating circuit coupled to pass the differentiated read head signal only in response to the phase encode signal when enabled by an envelope detector which indicates phase encoded data is being read.

13. The read circuit according to claim 1 above, further comprising a digital logic element coupled between the differentiator and the integrator circuit, the digital logic element having an output and a Schmitt trigger input which controls the output thereof and permits the output to respond to a low to high input change only when the input exceeds a first, relatively high, threshold and permits the output to respond to a high to low input change only when the input decreases below a second, relatively low, level.

14. The read circuit according to claim 13 above, further comprising a low pass filter having an input coupled to receive the differentiated read head signal and an output connected to the Schmitt trigger input of the digital logic element.

15. A read circuit for selectively processing phase encoded and NRZI information generated by a read head of a digital magnetic tape transport, the read circuit comprising:

a differentiating circuit connected to receive and differentiate a read head signal;

a squaring circuit connected to receive and square the differentiated read head signal;

a first EXCLUSIVE-OR gate having one input coupled to receive the squared differentiated signal, a second input coupled to receive a reverse signal which indicates that reading is occurring in a phase encoded format while tape is moving backwards, and an output;

a first inverter having an input coupled to the output of the first EXCLUSIVE-OR gate and an output;

a second EXCLUSIVE-OR gate having a first input coupled to the first inverter, a second input connected to a Q output of a toggling flip-flop and an output;

an intergrating circuit coupled to integrate a signal output by the second EXCLUSIVE-OR gate and generate an integrated differentiated read head signal as an output;

a latching flip-flop connected to latch a logic 1 data signal when clocked by a high to low transition of a signal output by the second EXCLUSIVE-OR gate while the integrated differentiated read head signal exceeds a selected threshold, the latching flip-flop being further coupled to be reset by a reset signal;

a first gating circuit coupled to pass an output from the latching flip-flop only when enabled by an NRZI signal indicating that information is being read from magnetic tape in an NRZI format;

a level detector circuit connected to generate an output signal when a read head signal exceeds a first threshold magnitude with a first polarity while enabled by a Q output of a toggling flip-flop and to generate an output signal when a read head signal exceeds a second threshold magnitude with a second polarity while enabled by a Q output of a toggling flip-flop;

a toggling flip-flop connected to successively toggle in the absence of an output signal from the level detector circuit, the toggling flip-flop having a Q output coupled to enable first polarity level detection by the comparator circuit and also coupled to the second input of the second EXCLUSIVE-OR gate and a Q output coupled to enable second polarity level detection by the level detection circuit; the toggling flip-flop having both its Q and Q outputs active in response to a phase encode signal which indicates the reading of information from magnetic tape in a phase encoded format;

an envelope detector coupled to indicate by an output signal the appearance of signals at the output of the level detector which are consistent with the reading of phase encoded data from magnetic tape;

and a second gating circuit coupled to pass signals appearing at the output of the second EXCLUSIVE-OR gate only when enabled by an output signal from the envelope detector and by the phase encode signal.

16. The read circuit according to claim 15 above, wherein the integrator circuit includes a capacitor which is connected to charge relatively slowly in response to a logic one output from the second EXCLUSIVE-OR gate and discharge relatively rapidly in response to a logic zero output from the second EXCLUSIVE-OR gate.

17. A read circuit for selectively reading information from digital magnetic tape which is recorded in either a standard 1600 bpi phase encoded format or a standard 800 bpi NRZI format, the read circuit comprising: a differentiating circuit coupled to differentiate a read head signal and generate a differentiated read head signal as an output; a latch circuit coupled to generate and hold an NRZI output data signal when the differentiated read head signal changes polarity after assuming a given polarity for at least a predetermined minimum period of time, the latch being selectively cleared by a reset signal; the output of the latch being available as an NRZI data signal and the differentiated read head signal being available as a phase encoded data signal.

18. The read circuit according to claim 17 above, wherein the differentiator circuit includes a high gain amplifier which amplifies and clips the derivative of the read head signal before outputting the amplified and clipped derivative as the differentiated read head signal.

19. The read circuit according to claim 18 above, further comprising a first gating circuit coupled to pass the NRZI output data signal only when enabled by an NRZI signal indicating the reading of data in an 800 bpi NRZI format and a second gating cirucit coupled to pass the differentiated read head signal only when enabled by a phase encode signal indicating the reading of data in a 1600 bpi phase encoded format.

20. A read circuit for use in a digital magnetic tape transport having a read head which detects flux transitions on magnetic tape, the read circuit comprising:

a differentiator responsive to a read head signal which generates a differentiated read head signal as an output;

a gating circuit having first and second inputs and an output generating a binary output signal which changes with each change of one of the first and second inputs relative to the other, the first input being a Schmitt trigger input which changes from low to high at a first, relatively high threshold, and changes from high to low at a second, relatively low threshold;

a filter having an input coupled to receive the differentiated read head signal and an output coupled to drive the first input of the gating circuit, the filter circuit permitting successive changes in the first input only with a predetermined minimum time therebetween,

means for changing the second input at a sufficiently high rate that at least two changes in the second input occur for each change in the first input;

means for inhibiting changes in the second input during the occurrence of a data pulse on the read head signal;

an integrator circuit coupled to receive and intergrate the binary output signal from the gating circuit, the integrator circuit generating an integrated, differentiated read head signal as an output;

a latch coupled to be set at the occurrence of a transition of the binary output signal from the gating circuit when the magnitude of the integrated differentiated read head signal is greater than a predetermined threshold magnitude.

21. The read circuit according to claim 20 above, wherein the filter permits successive changes in the first input only with a predetermined minimum time of at last one-twentieth of the nominal time between adjacent data bits.

Other info:

Inventors: Gray, Martin D. (Sierra Madre, CA, US)

Application Number: 538532
Filing Date: 1975-01-06
Publication_date: 1976-03-30
Assignee: C. J. Kennedy Company (Altadena, CA)
Primary Class(es): 360/40 360/41, 360/42
Other Classes:
US Patent Ref:

3581297

May, 1971

Behr et al.

360/40.

Other Refs:
Primary Examiner: Canney, Vincent P.
Assistant Examiner:
Attorney: Fraser and Bogucki