Title: Differential amplifier

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Claims: What is claimed is:

1. A differential amplifier comprising:

a. MOSFET constant current source means for setting an operating current level;

b. differential input means, coupled to said MOSFET constant current source means, having a first input terminal and a second input terminal for receiving two input signals to be compared, said differential input means comprising MOSFET devices of a first conductivity type;

c. load means comprising MOSFET active load devices of a second conductivity type opposite to said first conductivity type, coupled to said differential input means and coupled to one or more output terminals for producing an output signal responsive to said differential input means, said output terminal having a quiescient operating point determined by said operating current level;

d. load bias means coupled to said output terminals and said active loads for generating a compensating response to variations in said operating current level to maintain said quiescient operating point while also maintaining balanced operation of said output signal.

2. A differential amplifier as recited in claim 1, and further including:

a source of potential having at least a first and a second voltage level; and

a MOSFET biasing network connected between said first and second level of potential for providing a reference voltage;

said MOSFET constant current source means responsive to said reference from said biasing network for providing a constant current.

3. A differential amplifier as recited in claim 1, wherein said differential input means comprises:

a first input device having source, drain and gate electrodes;

a second input device having source, drain and gate electrodes;

said source electrodes of said first and second input devices being connected together and being coupled to said constant current source means;

said gate electrode of said first input device being adapted to receive a first input signal to be compared;

said gate electrode of said second input device being adapted to receive a second input signal to be compared; and

said first input device and said second input device being MOSFETs of said first conductivity type.

4. A differential amplifier as recited in claim 2, wherein said biasing network comprises:

an N-channel MOSFET device having source, drain and gate electrodes;

a first P-channel MOSFET device having source, drain and gate electrodes;

a second P-channel MOSFET device having source, drain and gate electrodes;

said source electrode of said N-channel device being connected to said first voltage level;

said gate electrode of said N-channel device being connected to said drain electrode of said N-channel device and said drain electrode of said first P-channel device and being further connected to said gate electrode of said first P-channel device;

said source electrode of said first P-channel device being connected to said drain electrode and said gate electrode of said second P-channel MOSFET device;

said source electrode of said second P-channel device being connected to said second voltage level; and

said junction of said gate electrode and drain electrode of said second P-channel device furnishing a reference current.

5. A differential amplifier as recited in claim 2, wherein said biasing network comprises:

an N-channel MOSFET device biasing source, drain and gate electrodes;

a first P-channel MOSFET device having source, drain and gate electrodes;

said source electrode of said N-channel device being connected to said first voltage level;

said gate electrode of said N-channel device forming a junction with said drain electrode of the same device and that junction being connected to said drain electrode of said first P-channel device;

said gate electrode of said first P-channel device being adapted to receive an input offset and bias adjust signal;

said source electrode of said first P-channel device being connected to the junction of said gate electrode and said drain electrode of said second P-channel device;

said source electrode of said second P-channel device being connected to said second voltage level; and

said junction of said gate electrode and drain electrode of said second P-channel device furnishing a reference current.

6. A differential amplifier as recited in claim 2, wherein said biasing network comprises:

a variable resistor having a first and a second terminal, said first terminal being connected to said first voltage level;

a P-channel MOSFET device having source, drain and gate electrodes;

said second terminal of said resistor being connected to a junction of said gate electrode and said drain electrode of said P-channel device;

said source electrode of said P-channel device being connected to said second voltage level; and said junction being a source of reference current.

7. A differential amplifier as recited in claim 2, wherein said biasing network comprises:

a first P-channel device having source, drain and gate electrodes;

a second P-channel device having source, drain and gate electrodes;

said drain electrode of said first P-channel device being connected to ground potential;

said gate electrode of said first P-channel device being adapted to receive an input offset and bias adjust signal;

said source electrode of said first P-channel device being connected to a junction of said drain electrode and said gate electrode of said second P-channel device;

said source electrode of said second P-channel device being connected to said second voltage level; and

said junction being a source of reference current.

8. A differential amplifier as recited in claim 2, wherein said constant current source comprises:

a first P-channel device having source, drain and gate electrodes;

said source electrode being connected to said second voltage level;

said drain electrode connected to said input stage for furnishing a constant current to said input stage; and

said gate electrode of said first P-channel device responsive to the output of said biasing network.

9. A differential amplifier as recited in claim 8, and further including:

a resistor connected in series between said source electrode of said first P-channel device and said second voltage level; and

a resistor connected in series between said MOSFET biasing network and said second voltage level.

10. A differential amplifier as recited in claim 8, and further including:

a second P-channel device having source, drain and gate electrodes;

said gate electrode of said second P-channel device being connected to said gate electrode of said first P-channel device;

said drain electrode of said second P-channel device being connected to said drain electrode of said first P-channel device; and

said source electrode of said second P-channel device being connected to said source electrode of said first P-channel device.

11. A differential amplifier as recited in claim 3, and further including:

a source of potential having at least a first and a second voltage level.

12. A differential amplifier as recited in claim 11, wherein said load means comprises:

a first load device having source, drain and gate electrodes;

a second load device having source, drain and gate electrodes;

said source electrode of said first load device being connected to said source electrode of said second load device and to said first voltage level;

said drain electrode of said first load device being connected to said drain electrode of said first input device for forming a first output terminal;

said drain electrode of said second load device being connected to said drain electrode of said second input device for forming a second output terminal;

said gate electrode and said drain electrode of said first load device and said gate electrode and said drain electrode of said second load device each being coupled to said load bias means; and

said first load device and said second load device each being MOSFETs of said second conductivity type.

13. A differential amplifier as recited in claim 12, wherein said load bias means comprises:

a first resistor connected between said gate electrode of said first load device and said drain electrode of said same device;

a second resistor connected between said gate electrode of said second load device and said drain electrode of said same device; and

a conductor connecting said gate electrode of said first load device and said gate electrode of said second load device.

14. A differential amplifier as recited in claim 12, wherein said load bias means comprises:

a. a conductor interconnecting said drain electrode of said first load device, said gate electrode of said same device and said gate electrode of said second load device.

15. A differential amplifier as recited in claim 13, wherein said MOSFET devices of a first conductivity type are P-channel MOSFETs and wherein said MOSFET active load devices of a second conductivity type are N-channel MOSFETs.

16. A differential amplifier as recited in claim 14, wherein said MOSFET devices of a first conductivity type are P-channel MOSFETs and wherein said MOSFET active load devices of a second conductivity type are N-channel MOSFETs.

17. A differential amplifier as recited in claim 16, and further comprising:

a third N-channel load device having source, drain and gate electrodes;

a fourth N-channel load device having source, drain and gate electrodes;

said source electrode of said third N-channel load device being connected to said drain electrode of said first N-channel load device, and said gate electrode of said third N-channel load device being connected to said drain electrode of said first P-channel input device; and

said source electrode of said fourth N-channel load device being connected to said drain electrode of said second N-channel load device and said gate electrode of said fourth N-channel load device being connected to said drain electrode of said third N-channel load device, and said drain electrode of said third N-channel device being connected to said drain electrode of said P-channel input device.

Other info:

Inventors: Hsiao, Perng (Tempe, AZ, US)
Musa, Fuad H. (Tempe, AZ, US)

Application Number: 505101
Filing Date: 1974-09-11
Publication_date: 1976-03-30
Assignee: Motorola, Inc. (Chicago, IL)
Primary Class(es): 330/253 330/257, 330/261
Other Classes:
US Patent Ref:

3569849	Mar, 1971	Cassidy	330/30.
3581226	May, 1971	Perkins	330/30.
3660773	May, 1972	Free	330/30.
3667063	May, 1972	Boyd et al.	330/30.
3852679	Dec, 1974	Schad, Jr.	330/30.

Other Refs:
Primary Examiner: Rolinec, R. V.
Assistant Examiner: Dahl, Lawrence J.
Attorney: Weiss; Harry M., Hoffman; Charles R.