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Title: Variable-gain amplifier
Claims: What is claimed is: 1. A variable-gain amplifier comprising: semiconductor means provided with an input electrode connected to a source of high-frequency signals and with two further electrodes including a reference electrode whose potential relative to that of said input electrode determines the conductivity of said semiconductor means, one of said further electrodes being connected to a load; degenerative circuitry connected to said reference electrode for applying thereto a negative-feedback voltage; a PIN diode in said degenerative circuitry; biasing means for said PIN diode including an operational amplifier provided with an inverting input, a non-inverting input, an output, and a negative-feedback path connected between said output and inverting input thereof, said PIN diode being inserted in said negative-feedback path; and a source of gain-controlling voltage connected to one of the inputs of said operational amplifier. 2. A variable-gain amplifier as defined in claim 1 wherein said semiconductor means comprises a first and a second transistor stage each having a base, an emitter and a collector, said input electrode being the base of said first transistor stage, said reference electrode being the emitter of said first transistor stage, said degenerative circuitry forming part of an emitter-follower connection for said first transistor stage and being coupled to the emitter of said second transistor stage, the emitter of said first transistor stage being connected to the load via the emitter and collector of said second transistor stage. 3. A variable-gain amplifier as defined in claim 2 wherein said transistor stages are of the same conductivity type. 4. A variable-gain amplifier as defined in claim 1 wherein said source of gain-controlling voltage comprises an amplifier circuit with an exponential characteristic. 5. A variable-gain amplfier as defined in claim 4 wherein said source of gain-controlling voltage further comprises a temperature-compensating circuit preceding said amplifier circuit. 6. A variable-gain amplifier as defined in claim 5 wherein said amplifier circuit and said temperature-compensating circuit comprise a second and a third operational amplifier, respectively. 7. A variable-gain amplifier as defined in claim 6 wherein said amplifier circuit includes an input transistor connected to said second operational amplifier, said temperature-compensating circuit including a further transistor inserted in a negative-feedback connection of said third operational amplifier, said further transistor being provided with a control-voltage input. 8. A variable-gain amplifier as defined in claim 7 wherein said input transistor and said further transistor are connected in series-opposed relationship. 9. In a monopulse radar having two conjugate channels, the improvement wherein one of said channels includes a variable-gain amplifier comprising: semiconductor means provided with an input electrode connected to a source of high-frequency signal and with two further electrodes including a reference electrode whose potential relative to that of said input electrode determines the conductivity of said semiconductor means, one of said further electrodes being connected to a load; degenerative circuitry connected to said reference electrode for applying thereto a negative-feedback voltage; a PIN diode in said degenerative circuitry; biasing means for said PIN diode including an operational amplifier provided with an inverting input, a noninverting input, and output, and a negative-feedback path connected between said output and inverting input thereof, said PIN diode being inserted in said negative-feedback path; and a source of gain-controlling voltage connected to one of the inputs of said operational amplifier. 10. The programmable controller as recited in claim 9 in which said scanner circuit includes control means for alternately executing a data output sequence and a data input sequence, said control means being connected to said interrupt means, connected to said data in gate means and connected to said data out gate means, and being operable to enable said interrupt means and said data out gate means during said data output sequence, and to enable said interrupt means and said data in gate means during said data input sequence. Other info: Inventors: Berrod, Francois (Paris, FR) Puverel, Fernand (Paris, FR) Application Number: 407996 Filing Date: 1973-10-19 Publication_date: 1976-03-02 Assignee: Thomson-CSF (Paris, FR) Primary Class(es): 342/92 330/86, 330/145, 330/283, 330/284, 330/289, 342/149, 342/205 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Tubbesing, T. H. Assistant Examiner: Montone, G. E. Attorney: Ross; Karl F., Dubno; Herbert |
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