Title: Input/output connection arrangement for microprogrammable computer

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Claims: What is claimed is:

1. In a microprocessor comprising: a control memory for storing control words at addressable locations, means for addressing said control memory, a first bus, a second bus and a third bus;

a. an input/output device external to said microprocessor and connected to said first, second and third buses, said input/output device having an address,

b. means for interrupting the means for addressing said control memory,

c. means responsive to said means for interrupting for modifying the address of said control memory to a desired address,

d. means associated with said input/output device for placing said address of said input/output device on said first bus,

e. means associated with said input/output device for placing input signals on said second bus,

f. means responsive to a control word at said desired address for utilizing said first bus input signals for identifying said input/output device, and

g. means for executing said control word at said desired address to operate upon said second bus input signals.

2. A microprocessor as set forth in claim 1 further comprising an arithmetic unit connected between said first and second buses and said third bus, wherein said arithmetic unit performs an arithmetic operation on said data of said second bus and places the result thereof on said third bus.

3. A microprocessor as set forth in claim 2 wherein said data is received from said third bus by said input/output device.

4. A microprocessor as set forth in claim 1 further comprising a logic unit connected between said first and second buses and said third bus, wherein said logic unit performs a logical operation on said data of said second bus and places the result thereof on said third bus.

5. A microprocessor as set forth in claim 2 wherein said data is received from said third bus by said input/output device.

6. A microprocessor comprising: a control memory for storing control words at addressable locations, means for addressing said control memory, a clock for generating a clock signal, a first bus, and a second bus, an addressable element connected to said first and second buses;

a. an input device external to said microprocessor,

b. means in said input device for providing an interrupt signal to interrupt said means for addressing said control memory, to initiate operation of an input/output routine,

c. means in said microprocessor for producing a response to said interrupt signal,

d. means in said input device for, in response to said interrupt response, placing data on said first bus and for placing an address of said addressable element on said second bus, and

e. means responsive to said clock signal for storing said data in said addressable element.

7. A microprocessor as set forth in claim 6 wherein said addressable element is a register block.

8. A microprocessor as set forth in claim 6 wherein said addressable element is a random access memory.

9. A microprocessor as set forth in claim 6 further comprising a third bus, means in said microprocessor for generating output signals on said third bus, an output device external to said microprocessor and connected thereto by said third bus and means within said output device for providing a destination for signals on said third bus.

10. A microprocessor as set forth in claim 9 further comprising:

a. means responsive to a clock signal for placing an address of said addressable element on said second bus, and

b. further means responsive to said clock signal for placing the contents of said addressable element at said address on said third bus.
Other info:

Inventors: Garlic, Richard A. (Irvine, CA, US)

Application Number: 428597
Filing Date: 1973-12-16
Publication_date: 1976-02-10
Assignee: Xerox Corporation (Stamford, CT)
Primary Class(es): 710/48
Other Classes:
US Patent Ref:

3462744	Aug, 1969	Tomasulo	340/172.
3517171	Jun, 1970	Avizienis	340/172.
3646522	Feb, 1972	Furman	340/172.
3689895	Sep, 1972	Kitamura	340/172.
3698007	Oct, 1972	Malcolm	340/172.
3702988	Nov, 1972	Haney	340/172.
3737861	Jun, 1973	O'Neill	340/172.
3745532	Jul, 1973	Erwin	340/172.
3748649	Jul, 1973	McEdwen	340/172.
3753236	Aug, 1973	Flynn	340/172.
3757306	Sep, 1973	Boone	340/172.
3761893	Sep, 1973	Morley	340/172.
3813651	May, 1974	Yamada	340/172.
3815099	Jun, 1974	Cohen	340/172.
3815104	Jun, 1974	Goldman	340/172.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Thomas, James D.
Attorney: Ralabate; James J., Weiss; Franklyn C., Sarli; Anthony J.