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Title: Amplifier for analogue signal samples with automatic gain control, and circuit for digitisation of such samples
Claims: We claim: 1. An electronic device for floating point digitisation of samples of analogue signals of constant definite polarity, comprising: amplifier means operative in a first state with a first predetermined gain from a signal input to an output, and in a second state for selectively supplying on its output either the difference between its signal input amplified by a second gain and a quantification value, or only its signal input amplified by said second gain, depending upon a polarity control; delay means having an input and an output adapted to be coupled to said output and said signal input of the amplifier means, respectively, for controllably re-circulating the output thereof after a time interval as a signal input to be re-amplified by the amplifier means; comparator means coupled to the output of the amplifier means and operative in first and second states for indicating when the output of the amplifier means exceeds first and second reference values, respectively; and control means, effective upon application of a sample of an analogue signal to said signal input of the amplifier means, for operating said amplifier means and said comparator means in their respective first states, while repetitively controlling said delay means to re-circulate the output of the amplifier means unless said comparator means indicates that the output of the amplifier means exceeds the first reference value, and for subsequently operating said amplifier means and comparator means in their respective second states, while repetitively controlling said delay means to re-circulate the output of the amplifier means a selected number of times and each time supplying to said amplifier means a polarity control depending upon the indication of said comparator means. 2. A device according to claim 1, wherein the amplifier means comprises a differential amplifier whose non-inverting input is the signal input, whose output is the output of the amplifier circuit, and whose inverting input is connected to the output by a feedback resistance, and coupling means coupling said inverting input in the first state through a resistance to ground, the ratio of the value of the last-named resistance to the value of the feedback resistance being in relation to the said first gain, and said coupling means coupling said inverting input in the second state through a resistance either to a source of a quantification signal representing said quantification value or to ground, depending upon said polarity control, the ratio of the value of the last-named resistance to the value of the feedback resistance being in relation go the second gain. 3. An electronic device according to claim 2, comprising an analogue signal input path and controllable switching means for selectively coupling the signal input of the amplifier means either to the input path or to the output of the delay means, wherein said control means is sequentially operative in a preliminary state and in an effective state for controlling said controllable switching means to couple the signal input of the amplifier means to the input path and to the output of the delay means, respectively, thereby permitting sampling of the analogue signal and subsequent digitisation of each sample with floating point. 4. An electronic device according to claim 3, wherein the coupling means of the inverting input of the differential amplifier to ground each comprises a controllable switch in series on each resistance, and said control means is also operative in said preliminary and effective states for opening and closing respectively, said series controllable switch. 5. A device according to claim 1, wherein the delay means comprises in series a first controllable switch, a first static analogue store, an ampllifier, a second controllable switch, and a second static analogue store, and the control means is effective for normally closing the first controllable swithc and opening the second one, and for repetitively opening the first controllable switch and closing the second one to make the re-circulation, the re-circulation, being repeated in the first state unless the output of the amplifier means exceeds the first reference value, and being made a predetermined number of times in the second state. 6. A device according to claim 5, wherein said comparator means is coupled to the output of the amplifier means through one of the said static analogue stores. 7. A device according to claim 5, wherein the amplifier of the delay means has unit gain, and the closure time of the second switch defines said time interval. 8. A device according to claim 1, wherein said delay means includes in series a first controllable switch, a first static analogue store, another amplifier means, a second controllable switch, and a second static analogue store, the closure times of the first and second controllable swtiches alternately defining said time interval, said other amplifier means being effective in a first state to provide a third predetermined gain from a signal input to an output, and in a second state for selectively supplying on its output either the difference between its signal input amplified by said second gain and said quantification value, or only its signal input amplified by said second gain, depending upon another polarity control, the device further comprising another comparator means coupled to said ooutput of the said other amplifier means and operative in first and second states for indicating when said output of said other amplifier means exceeds a third reference value and said second reference value, respectively, and wherein the control means is alternately effective for closing the first controllable switch and opening the second one while monitoring said comparator means, and for opening the first controllable switch and closing the second one while monitoring said other comparator means, the operation being repeated in the first state unless one of the comparator means indicates that its reference value has been exceeded, and being made a predetermined number of times in the second state, while alternately applying to said amplifier means and said other amplifier means a polarity control depending upon the indication of said other comparator means and said comparator means, respectively. 9. A device according to claim 8, wherein the first and third gains of the amplifier means are equal and the first and third reference values of the comparator means are the same. 10. A device according to claim 1, wherein the delay means comprises two paths in parallel, each having in series a controllable input switch, a static analogue store, and a controllable output switch, and wherein the control means is effective for alternately controlling the switches so that at any instant the input switch of only one of the paths is closed and that, in each path, the output switch is closed only when the input switch is opened, the closure time of the input switches alternately defining the aforesaid time interval, the operation being repeated in the first state unless the comparator means indicates that its reference value is being exceeded, and being made a predetermined number of times in the second state. 11. A device according to claim 1, wherein the delay means comprises a delay line having amplification means for giving it unit gain, the transit time through the delay line defining the aforesaid time interval. 12. A device according to claim 1, having an output path coupled to the output of the comparator means for supplying serial information about the overall gain applied to each sample of analogue signal in said first state, and for subsequently supplying serial information about the digital value of each sample of the analogue signal, in the second state. 13. A device according to claim 1, wherein said second reference value of the comparator means equals said quantification value. 14. The combination of a source of analogue signal samples with a floating point digitizer device according to claim 1, for suplying repetitively a floating point digital signal representative of a sample of the analogue signals of said source. 15. An electronic device for floating point digitisation of analogue signals of any polarity, comprising: amplifier means operative in a first state with a first predetermined gain from a signal input to an output, and in a second state for selectively supplying on its output its signal input amplified by a second gain either minus or plus a quantification value, depending upon a polarity control; delay means having an input and an output adapted to be coupled to said output and said signal input of the amplifier means, respectively, for controllably re-circulating the output thereof after a time interval as a signal input to be reamplified by the amplifier means; comparator means coupled to the output of the amplifier means and operative in first and second states for indicating when the output of the amplifier means exceeds first and second reference values, respectively; and control means, effective upon application of a sample of an analogue signal to said signal input of the amplifier means, for operating said amplifier means and said comparator means in their respective first states, while repetitively controlling said delay means to re-circulate the output of the amplifier means unless said comparator means indicates that the output of the amplifier means exceeds the first reference value, and for subsequently operating said amplifier means and comparator means in their respective second states, while repetitively controlling said delay means to re-circulate the output of the amplifier means a selected number of times and each time supplying said amplifier means with a polarity control depending upon the indication of said comparator means. 16. A device according to claim 15, wherein the amplifier means comprises a differential amplifier whose non-inverting input is the signal input, whose output is the output of the amplifier circuit, and whose inverting input is connected to the output by a feedback resistance, and coupling means coupling said inverting input in the first state through a resistance to ground, the ratio of the value of the last-named resistance to the value of the feedback resistance being in relation to the first gain, and said coupling means coupling said inverting input in the second state through a resistance to a source of a quantification signal having an amplitude representing said quantification value and one or the other polarity depending upon polarity control, the ratio of the value of the last-named resistance to the value of the feedback resistance being in relation to the second gain. 17. An electronic device according to claim 16, comprising an analogue signal input path and controllable switching means for selectively coupling the signal input of the amplifier means either to the input path or to the output of the delay means, wherein said control means is sequentially operative in a preliminary state and in an effective state for controlling said controllable switching means to couple the signal input of the amplifier means to the input path and to the output of the delay means, respectively, thereby permitting sampling of the analogue signal and subsequent digitisation of each sample with floating point. 18. An electronic device according to claim 17, wherein the coupling means of the inverting input of the differential amplifier to ground each comprises a controllable switch in series on each resistance, and said control means is also operative in said preliminary and effective states for opening and closing respectively, said series controllable switch. 19. A device according to claim 15, wherein the delay means comprises in series a first controllable switch, a first static analogue store, an amplifier, a second controllable switch and a second static analogue store, and the control means is effective for normally closing the first controllable switch and opening the second one, and for repetitively opening the first controllable switch and closing the second one to make the re-circulation, the re-circulation being repeated in the the first state unless the output of the amplifier means exceeds the first reference value, and being made a predetermined number of times in the second state. 20. A device according to claim 19, wherein the amplifier of the store circuit has unit gain, the closure time of the second switch defining the aforesaid time interval. 21. A device according to claim 19, wherein said comparator means is coupled to the output of the amplifier means through one of the said static analogue stores. 22. A device according to claim 15, wherein said delay means includes in series a first controllable switch, a first static analogue store, another amplifier means a second controllable switch, and a second static analogue store, the closure times of the first and second controllable switches alternately defining said time interval, said other amplifier means being effective in a first state to provide a third predetermined gain from a signal input to an output, and in a second state for selectively supplying on its output its signal input amplified by said second gain either minus or plus said quantification value, depending upon another polarity control, the device further comprising another comparator means coupled to said output of the said other amplifier means and operative in first and second states for indicating when said output of said other amplifier means exceeds a third reference value and said second reference value, respectively, and wherein the control means is alternately effective for closing the first controllable switch and opening the second one while monitoring said comparator means, and for opening the first controllable switch and closing the second one while monitoring said other comparator means, the operation being repeated in the first state unless one of the comparator means indicates that its reference value has been exceeded, and being made a predetermined number of times in the second state, while alternately applying to said amplifier means and said other amplifier means a polarity control depending upon the indication of said other comparator means and said comparator means, respectively. 23. A device according to claim 22, wherein the first and third gains of the amplifier means are equal and the first and third reference values of the comparator means are the same. 24. A device according to claim 15, wherein the delay means comprises two paths in parallel, each having in series a controllable input switch, a static analogue store, and a controllable output switch, and wherein the control means is effective for alternately controlling the switches so that at any instant the input switch of only one of the paths is closed and that, in each path, the output switch is closed only when the input switch is opened, the closure time of the input switches alternately defining the aforesaid time interval, the operation being repeated in the first state unless the comparator means indicates that its reference value is being exceeded, and being made a predetermined number of times in the second state. 25. A device according to claim 15, having an output path coupled to the output of the comparator means for supplying serial information about the overall gain applied to each sample of analogue signal in said first state, and for subsequently supplying serial information about the digital value of each sample of the analogue signal, in the second state. 26. A device according to claim 15, wherein the amplifier means is controllably switchable into unit gain and the control means is adapted to switch the amplifier means into unit gain at the commencement of the second state for determination of sign. 27. A device according to claim 15, wherein said second reference value of the comparator means is zero. 28. The combination of a source of analogue signals with a floating point digitiser device according to claim 15, for supplying repetively a floating point digital signal representative of a sample of the analogue signals of said sorce. Other info: Inventors: Angelle, Philippe (Thouare, FR) Lefevre, Georges (Nantes, FR) Application Number: 322333 Filing Date: 1973-01-10 Publication_date: 1976-02-03 Assignee: Societe D'Etudes, Recherches Et Constructions Electroniques Sercel (Carquefou, FR) Primary Class(es): 341/139 324/115, 330/9, 330/127, 341/158 Other Classes: US Patent Ref:
Other Refs: Primary Examiner: Miller, Charles D. Assistant Examiner: Attorney: Levine; Alan H. |
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