Title: Solid state associative processor organization

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Claims: What is claimed is:

1. A digital computer organization, comprising:

a memory array comprised of a plurality of address line encoded binary solid state memory modules and containing data bit storage elements wherein data may be stored as bit-comprised words with bit B of module M containing bit B of word W in accordance with the formula M = B .sym. W and wherein B, M, and W are n-element binary vectors, respectively unique for each bit, module, and word, and where n is an integer greater than 1;

a logic circuit means connected to the memory array for simultaneously performing logic and arithmetic operations on all accessed data bits;

a coding circuit; and

permuting circuit means connected to the coding circuit and between the memory array and logic circuit means for ordering the lineal order of data into and out of the memory array in accordance with the output of the coding circuit.

2. The digital computer organization as recited in claim 1 wherein said logic circuit means comprises a plurality of identical circuits, each capable of performing 16 unique arithmetic and logic operations.

3. The digital computer organization as recited in claim 2 wherein said logic circuit means includes three latching means, a first latching means for receiving and storing bits of data, a second latching means for storing intermediate results from said logic operations, and a third latching means for masking the accessing of the data storage bits of the memory array.

4. The digital computer organization as recited in claim 3 wherein said permuting circuit means is connected to said coding circuit and includes a plurality of data selectors having data input lines, one data output line, and channel select input lines for controlling the transfer of data from the input lines to the output line.

5. The digital computer organization as recited in claim 4 wherein the coding circuit applies an n-element mode of access code X to the channel select input lines to control the passage of data through the permuting circuit means from a data source position P to a data destination M in accordance with the formula P = M .sym. X where M and P are n-element binary vectors unique for each data source position and each data destination.

Other info:

Inventors: Batcher, Kenneth E. (Stow, OH, US)

Application Number: 457155
Filing Date: 1974-04-01
Publication_date: 1976-02-03
Assignee: Goodyear Aerospace Corporation (Akron, OH)
Primary Class(es): 712/10
Other Classes:
US Patent Ref:

3189879	Jun, 1965	MacIntyre et al.	340/172.
3277449	Oct, 1966	Shooman	340/172.
3287703	Nov, 1966	Slotnick	340/172.
3339181	Aug, 1967	Singleton et al.	340/172.
3473160	Oct, 1969	Wahlstrum	340/172.
3535694	Oct, 1970	Anacker et al.	340/172.
3618041	Nov, 1971	Horikoshi	340/172.
3647348	Mar, 1972	Smith et al.	340/172.
3670308	Jun, 1972	Tutelman	340/172.
3681761	Aug, 1972	Schuenemann et al.	340/172.
3681763	Aug, 1972	Meade et al.	340/173.
3685020	Aug, 1972	Meade	340/172.
3757312	Sep, 1973	Shore et al.	340/172.
3763472	Oct, 1973	Sharp	340/172.
3800289	Mar, 1974	Batcher	340/172.
3812467	May, 1974	Batcher	340/172.
3863233	Jan, 1975	Eddey et al.	340/172.

Other Refs:
Primary Examiner: Shaw, Gareth D.
Assistant Examiner: Sachs, Michael C.
Attorney: Oldham & Oldham