Title: Rate signal generator circuit

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1. A rate signal generating circuit for determining the rate of recurrence of electrical signals, said circuit comprising means for sensing said electrical signals, a capacitor, charging circuit means connected between said sensing means and said capacitor to charge said capacitor to a predetermined voltage level during a predetermined time interval in response to the sensing of one of said electrical signals, a plurality of resistors connected in series and coupled to said capacitor to provide a discharge path therefor, electronic switch means connected to said resistors and said capacitor for shorting selected said resistors in response to predetermined charged voltages across said capacitor, wherein said capacitor discharges to define a rate function, and sample and hold means coupled to said capacitor and said sensing means for actuation by each successive said electrical signal to provide an output voltage proportional to the rate of recurrence of said signals.

2. A rate signal generator as set forth in claim 1 wherein said plurality of resistors connected in series comprises at least three resistors, and wherein said electronic switch means comprises first and second FET switches connected in parallel with respective ones of said three resistors, said FET switches having gate electrodes, said electronic switch means further including first and second threshold detector means, each having first inputs connected to said capacitor, and having second inputs for connection to respective different sources of bias voltages, said threshold detector means each having outputs connected respectively to said gate electrodes of said FET switches, wherein said first and second threshold detector means are energized sequentially by a discharging voltage across said capacitor to sequentially actuate said FET switches, thereby altering the said discharge resistance path connected to said capacitor.

3. A rate signal generator circuit as set forth in claim 2 wherein said sample and hold means comprises a buffer amplifier having an output, and having an input coupled to said capacitor, an FET sample switch, a signal storing capacitor connected through said FET sample switch to the output of said buffer amplifier, said FET sample switch having a gate electrode connected for control to said sensing means, and an FET output transistor connected to said signal storing capacitor to provide said output voltage proportional to the rate of recurrence of said signals.

Other info:

Inventors: Hughes, Philip A. (Littleton, CO, US)

Application Number: 448293
Filing Date: 1974-03-05
Publication_date: 1976-02-03
Assignee: Sandoz, Inc. (E. Hanover, NJ)
Primary Class(es): 327/93 327/114
Other Classes:
US Patent Ref:

3740586

Jun, 1973

Banks et al.

307/271.

Other Refs:
Primary Examiner: Brody, Alfred L.
Assistant Examiner:
Attorney: Sharkin; Gerald D., Honor; Robert S., Jewell; Walter F.