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Title: Dual delay line storage sound signal processor
Claims: I claim: 1. A processor for analog electric signals representing coded audible signals such as speech or the like, said electric signals being analog representations of said audible signals with the frequency components of said electric signals related by a given factor to the frequency components of said audible signals comprising: two similar analog shift register delay lines having input terminals coupled to a source of said analog electric signals for serially entering sequential analog samples of said analog electric signals at said input terminals thereof and having output terminals for serially removing said analog samples from said delay lines at said output terminals; said input terminals coupled to said source of analog signals through input switch means operable to supply said analog signals alternately to said input terminals; and said output terminals coupled through output switch means operable alternately to pass said analog samples emerging from said delay lines; first and second predetermined frequency clock sources for clocking said delay lines; means for controlling said delay lines alternately from said clock frequency sources for simultaneous alternate serial entry and removal of said analog samples at said first and second clock frequencies, respectively, to produce predetermined frequency transformation for signals made up of the sequence of said analog samples emerging at said output terminals of said delay lines, said means for controlling said delay lines also controlling said input and output switches to input one said line while outputting the other said line and vice-versa; and analog signal processing means coupled to said output terminals of both said delay lines through said output switch means and responsive to said analog samples emerging alternately from said delay lines which have been subject to said predetermined frequency transformation for producing an output analog signal reproducible as an audible representation of said electric signals having frequency components altered by substantially the inverse of said factor to approximate the frequency components of said audible signals. 2. An analog speech compressor-expander for a recording reproduced at play-back speed greater or less than the recorded speed thereby producing a time and frequency altered signal comprising: two analog shift registers having input terminals, output terminals and clocking terminals; an input double throw switch means operable for alternately supplying said signal to said input terminals; an output double throw switch means operable for alternately supplying the signals from said output terminals to a common output line; a source of two clocking frequencies; double-pole double-throw switch means operable for alternately applying said two clocking frequencies to said clocking terminals; and control means for operating all of said switch means in unison to input one said line at one clock frequency while outputting the other said line at the other clock frequency and vice-versa, said two clocking frequencies having a ratio corresponding to the ratio of said recorded and playback speed to produce on said output line only a time altered but frequency restored signal replica of said recording. Other info: Inventors: Schiffman, Murray M. (Westport, CT, US) Application Number: 473437 Filing Date: 1974-05-28 Publication_date: 1976-02-03 Assignee: Cambridge Research and Development Group (Westport, CT); Greenberg; Sanford D. (Washington, DC); DT Liquidating Partnership (New York, NY); Schiffman; Murray M. (Westport, CT) Primary Class(es): 704/205 348/384.1, 360/8, 386/89, 386/101, 704/258 Other Classes: US Patent Ref:
Other Refs: Other References: IEEE Journal of Solid-State Circuits; Vol. 564, No. 3, June 1969, "Bucket Brigade Electronics . . .," by Sangster et al., pp. 131-136. Nature; Vol. 189, No. 4759, Jan. 14, 1961, pp. 117-119, "A Versatile Method for Short Term Spectrum Analysis . . .," by Gill. | |