Title: Signal generator comprising an addressable memory

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Claims: What is claimed is:

1. A signal generator, comprising:

an addressable memory having n separate input terminals for receiving the n-bits of an n-bit address word to address one of the 2.sup.n addressable registers therein each register storing an n-bit data word, the n bits of which are each coupled to a separate associated one of n separate output terminals;

a plurality of n-bit data words of differing values, said data words stored in consecutively addressed ones of said registers;

n separate feedback means for directly coupling each separate one of said n output terminals back to only a separate associated one of said n input terminals;

means enabling said memory to read out the data word stored in a first one of its registers for continuously and repetitively cycling said memory through its 2.sup.n registers by using the read out data word as the address word to address the next addressed register at the next memory cycle;

n separate output signal means coupled to each separate one of said n separate output terminals for generating, on each separate one of said n output signal means, n timing pulses of n differing frequencies.

2. The signal generator of claim 1 in which said n separate feedback means do not directly couple each separate one of said n output terminals to the separate associated one of said n input terminals, but each of said n separate feedback means includes similar delay means for decreasing the frequency of said memory cycle.

3. The signal generator of claim 1 in which each of said n separate feedback means includes delay means for decreasing the frequency of said memory cycle.

4. The signal generator of claim 1 further including:

a register having n states;

n separate conductors coupled to each separate one of said n separate output signal means for coupling each separate one of said n timing pulses to a separate associated one of the stages of said register.

5. A signal generator, comprising:

an addressable memory having n separate input terminals for receiving the n-bits of an n-bit address word to address one of the 2.sup.n addressable registers therein, each register storing an n-bit data word, the n bits of which are each coupled to a separate associated one of n separate output terminals;

a binary table of 2.sup.n n-bit data words of consecutively increasing values, said data words stored in consecutively addressed ones of said registers with a 1 stored in register address 0 and with a 0 stored in register address 2.sup.n -1;

n separate feedback means for directly coupling each separate one of said n output terminals back to only a separate associated one of said n input terminals;

means enabling said memory to read out the data word stored in a first one of its registers for continuously and repetitively cycling said memory through its 2.sup.n registers by using the read out data word as the address word to address the next addressed register at the next memory cycle, the frequency of said memory cycle being determined solely by the delay of the internal electronics of said memory;

n separate output signal means coupled to each separate one of said n separate output terminals for generating, on each separate one of said n output signal means, n timing pulses of n different frequencies.
Other info:

Inventors: Moore, III, Harry W. (Dryden, NY, US)

Application Number: 498789
Filing Date: 1974-08-19
Publication_date: 1976-01-27
Assignee: Sperry Rand Corporation (New York, NY)
Primary Class(es): 365/233
Other Classes:
US Patent Ref:

3772658

Nov, 1973

Sarlo

340/173.

Other Refs:
Primary Examiner: Fears, Terrell W.
Assistant Examiner:
Attorney: Grace; Kenneth T., Nikolai; Thomas J., Truex; Marshall M.