Title: A-C signal multiplying circuit by a ratio of whole numbers the numerator of which is greater than one and greater than the denominator

Do you think this is a good invention? Vote now:

Votes so far: For:(0) Against:(0)
Claims: I claim:

1. A frequency multiplier circuit for frequency-multiplying an a-c signal by a ratio of whole numbers wherein the absolute value of the numerator of said ratio is greater than the absolute value of the denominator of said ratio and greater than one comprising:

a. means for providing an a-c signal;

b. means for providing a clock-frequency-signal of frequency greater than said a-c signal, said clock-frequency-signal providing means having an output;

c. means for receiving and dividing the frequency of said a-c signal by a first predetermined whole number greater than one said receiving and dividing means having an output;

d. a differentiator circuit having an input and an output, said input being connected to said output of said means for receiving and dividing the frequency of said a-c signal by a first whole number greater than one;

e. a clock gate curcuit having a clock-frequency-signal input, a second input and an output, said clock-frequency-signal input being connected to said output of said means for providing a clock-frequency-signal;

f. a binary counter circuit having a first input, a second input, a first output, and a second output, said second input being connected to said output of said differentiator circuit, said first input being connected to said output of said clock gate circuit; and

g. a flip-flop circuit having a first input, a second input, and an output, said first input being connected to said second output of said binary counter circuit, said second input being connected to said output of said differentiator circuit, said output of said flip-flop circuit being connected to said second input of said clock gate circuit, the signal on the output of said differentiator circuit resets said binary counter circuit and said flip-flop circuit, then said flip-flop circuit enables said clock gate circuit passing said clock frequency signal to said binary counter circuit, after counting a predetermined second whole number of cycles of said clock frequency signal, said second whole number being greater than one and greater than said first whole number, said binary counter circuit clocks said flip-flop circuit, causing said flip-flop circuit to inhibit said clock gate circuit until said differentiator circuit resets said binary counter circuit and said flip-flop circuit, whereby for every cycle of said frequency-divided a-c signal, said second whole number of cycles of said clock-frequency-signal appears on said binary counter circuit first output, said second whole number of cycles of said clock-frequency-signal appearing on said binary counter circuit first output being said ratio-of-whole-numbers, frequency multiplied, a-c signal.

Other info:

Inventors: Linder, John L. (Las Cruces, NM, US)

Application Number: 516540
Filing Date: 1974-10-21
Publication_date: 1976-01-27
Assignee: The United States of America as represented by the Secretary of the Navy (Washington, DC)
Primary Class(es): 377/48 327/3, 327/40, 327/356, 377/39
Other Classes:
US Patent Ref:

3673391	Jun, 1972	Lougheed	328/38.
3753125	Aug, 1973	Ishikawa et al.	328/38.
3769597	Oct, 1973	Mayer	307/220.
3835396	Sep, 1974	Demos et al.	328/38.

Other Refs:
Primary Examiner: Miller, Jr., Stanley D.
Assistant Examiner: Anagnos, L. N.
Attorney: Sciascia; Richard S., St.Amand; Joseph M., Hollis; Darrell E.