Title: Multiplexed signal-sequence control system

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Claims: What is claimed is:

1. A multiplexed signal-sequence control system comprising:

1. first circuit means operative, when fully energized, to generate a multiplexed output signal comprising a plurality of component signals each representative of the presence or absence of a signal of the first class; and

2. second circuit means operative to receive a plurality of signals of the second class and, upon receiving a signal of the second class, further operative to fully energize said first circuit means and to process signals of the first and second classes in that order, and further operative to generate a control signal in response to (a) one or more signals of only the first class or only the second class, (b) unrelated signals of both the first and second classes, or (c) related signals of both the first and second classes occurring in an improper sequence.

2. The system according to claim 1 wherein said first circuit means comprises:

1. timing circuit means operative to generate first and second pulse trains, a plurality of gate signals and a plurality of timing signals;

2. gating circuit means comprising a plurality of gates each operative to sense a signal of the first class at an input terminal, and each further operative to pass said signal of the first class upon receiving one of said plurality of gate signals from said timing circuit means; and

3. detection circuit means operative to receive said first and second pulse trains from said timing circuit means and a composite input signal formed by the signals of the first class passed through said gating circuit means, and further operative in response thereto to generate said multiplexed output signal comprising a plurality of component signals each representative of the presence or absence of a signal of the first class.

3. The system according to claim 2 wherein said timing circuit means comprises:

1. high-frequency, square-wave generator means operative to generate a clock signal;

2. a plurality of flip-flop circuits connected in series and each operative to generate complementary output signals of progressively decreasing frequency, said first pulse train being generated by one of said plurality of flip-flop circuits;

3. first logic means operative to receive said clock signal from said high-frequency, square-wave generator means and the first outputs from said first and second flip-flop circuits, and further operative in response thereto to produce said second pulse train;

4.

4. second logic means operative to receive the first and second output signals from each of the third and fourth flip-flop circuits and, in response thereto, to generate said plurality of gate signals; and

5. third logic means operative to receive said second pulse train from said first logic means and said plurality of gate signals from said second logic means, and further operative to generate said plurality of timing

signals. 4. The system according to claim 3 wherein said first logic means comprises a NAND gate having first and second inputs connected to receive said clock signal from said high-frequency, square-wave generator means, having a third input connected to receive said first output of said first flip-flop circuit, and having a fourth input connected to receive said first output of said second flip-flop circuit, and an inverter having its input connected to the output of said NAND gate, said second pulse train being generated at the output of said inverter.

5. The system according to claim 3 wherein said second logic means comprises a plurality of series-connected NAND gate/inverter circuits.

6. The system according to claim 3 wherein said third logic means comprises a plurality of series-connected NAND gate/inverter circuits.

7. The system according to claim 5 wherein each of said plurality of gates forming said gating circuit means has a control terminal connected to the output of the associated NAND gate/inverter circuit of said second logic means, and the output terminals of said plurality of gates are connected through a common capacitance to said detection circuit means to provide said composite input signal thereto.

8. The system according to claim 2 wherein said detection circuit means comprises:

1. buffer amplifier means operative to receive said first pulse train from said timing circuit means and to generate energizing pulses in response thereto;

2. shock-excited oscillator means operative to receive said energizing pulses generated by said buffer amplifier means and the output of said gate means, and further operative to generate a high-frequency output during the null periods between the energizing pulses generated by said buffer amplifier means;

3. detector means operative to detect the envelope of the high-frequency output of said shockexcited oscillator means; and

4. gating means operative to receive said second pulse train from said timing circuit means and to pass the detected output of said detector means only when said detected output is coincident with a pulse in said second pulse train.

9. The system according to claim 8 wherein said shock-excited oscillator means is coupled through said gating circuit means to a plurality of antennae for detecting the presence or absence of one or more external impedances having a substantial capacitive and/or resistive component coupled to any of said antennae, in response to which said high frequency output generated by said shockexcited oscillator means is damped.

10. The system according to claim 1 wherein said second circuit means comprises:

1. power supply circuit means operative to receive standby power from an external source of power and normally operative to maintain said first circuit means partially de-energized, and further operative upon actuation to generate a power signal and a power output which fully energizes said first circuit means;

2. first monitor circuit means operative to receive a plurality of timing signals from said first circuit means and a plurality of signals of the second class and, in response to a signal of the second class, further operative to actuate said power supply circuit means to fully energize said first circuit means;

3. second monitor circuit means operative to receive said plurality of timing signals from said first circuit means, said power signal from said power supply circuit means, said second pulse train from said first circuit means, and said multiplexed output signal comprising a plurality of component signals each representative of the presence or absence of a signal of the second class and, in response thereto, to generate an intermediate signal in response to (1) one or more signals of only the first class or only the second class, (2) unrelated signals of both the first and second classes, and (3) related signals of both the first and second classes occurring in an improper sequence;

4. drive circuit means operative to receive said intermediate signal from said second monitor circuit means and, in response thereto, to generate said control signal; and

5. delay circuit means operative to receive the power output from said power supply circuit means and to delay the generation of said power signal for a predetermined period of time after the generation of said power output by said power supply circuit means.

11. The system according to claim 10 wherein said power supply circuit means comprises a plurality of inverters each having its input coupled to said first monitor circuit means to receive an associated one of said plurality of signals of the second class, and each having its output connected to an associated input terminal of a NAND gate, the output of said NAND gate being coupled to power switching means connected to said external source of power and operative in response to a logic high output from said NAND gate to generate said power output and said power signal.

12. The system according to claim 11 wherein said power switching means comprises a transistor having its collector connected to said external source of power, its emitter connected through a filter capacitance to ground, and its base connected to a voltage regulation circuit comprising a resistance and a zener diode connected in series between the output of said NAND gate and ground, said power output being developed at the emitter of said transistor, and said power signal being developed through a resistance connected between said emitter of said transistor and said first and second monitor circuit means and said delay circuit means.

13. The system according to claim 11 wherein said first monitor circuit means comprises a plurality of voltage divider means each including a pair of resistors connected from said external source of power through a switch at the junction of said pair of resistors to ground, said switch being normally open and having its low terminal connected to an associated one of a plurality of NAND gates and to an associated one of a plurality of said inverters in said power supply circuit means, each of said plurality of NAND gates also being operative to receive said plurality of timing signals from said first circuit means, the outputs of said plurality of NAND gates being connected to the associated input terminals of a NAND gate having its output terminal connected to control said power signal by either not shunting or by intermittently shunting said power signal.

14. The system according to claim 10 wherein said second monitor circuit means comprises:

1. a plurality of NAND gate pairs operative to receive said plurality of timing signals from said timing circuit means, said power signal from said power supply circuit means and said multiplexed otuput signal from said first circuit means, and operative in response thereto to generate a plurality of intermediate signals each of which is indicative of the occurrence of (1) one or more signals of only the first class or only the second class, (2) unrelated signals of both the first and second classes, and (3) related signals of both the first and second classes occurring in an improper sequence;

2. a NAND gate having its inputs connected to receive said plurality of intermediate signals from said plurality of NAND gate pairs;

3. inverter means operative to receive the output of said NAND gate;

4. an output NAND gate operative to receive the output of said inverter means as a first input;

5. power signal inverter means operative to receive said power signal from said power supply circuit means; and

6. an input NAND gate operative to receive said multiplexed output signal from said first circuit means, said second pulse train from said first circuit means, and the output of said power signal inverter, and to provide a second input to said output NAND gate.

15. The system according to claim 14 wherein each of said NAND gate pairs comprises first and second NAND gates, said first NAND gate having its output connected to a first input of said second NAND gate, the second input of said second NAND gate being connected to a first input of said first NAND gate, each of which receives an associated one of a plurality of said timing signals from said first circuit means, and said third input of said second NAND gate is connected to receive said power signal, the second input of said first NAND gate being connected to receive said multiplexed output signal from said first circuit means, and the third input of said first NAND gate being connected to the output of said second NAND gate, said intermediate signal being generated at the output of said second NAND gate.

16. The system according to claim 10 wherein said drive circuit means comprises:

1. a monostable multivibrator normally operative to provide a high output, and operative in response to a negative going intermediate signal from said second monitor circuit means to generate a low output for a predetermined period of time; and

2. transistor means operative to receive the output of said monostable multivibrator and to change the energization state of an external circuit in response to a change in the output of said monostable multivibrator.

17. The system according to claim 16 wherein said monostable multivibrator comprises:

1. a NAND gate having a first input terminal connected to receive said intermediate output from said second monitor circuit means;

2. a capacitance and a resistance connected in series from the output of said NAND gate to ground; and

3. inverter means having its input connected to the junction of said capacitance and resistance and having its output connected to a second input of said NAND gate, said control signal being developed at the output of said inverter means.

18. The system according to claim 16 wherein said transistor is maintained normally non-conductive by a high output from said monostable multivibrator, and said transistor is rendered conductive in response to a low output from said monostable multivibrator, which low output constitutes said control signal.

19. The system according to claim 12 wherein said delay circuit means comprises first and second diodes connected in series, with the anode of said first diode being connected to receive the power output of said power supply circuit means and the cathode of said second diode being connected to receive the power signal of said power supply circuit means, and a timing capacitance connected from the junction of the cathode of said first diode and the anode of said second diode to ground, said resistance connected from the emitter of said transistor in said power switching means and said timing capacitance forming an RC charging circuit operative to delay the development of said power signal for a predetermined period of time after the generation of said power output by said power supply circuit means.

20. In a vehicle having a plurality of seating stations, a plurality of seating belts each associated with one of said seating stations, an ignition/auxiliary power circuit, and a warning/disabling circuit, the improvement comprising:

normally partially de-energized mutliplexed signal-sequence control means operative to receive a plurality of signals of the first class indicating seat belt usage, and further operative to become fully energized either upon receiving a signal of the second class or upon actuation of the ignition/auxiliary power circuit, and operative when fully energized to actuate the warning/disabling circuit in response to (1) one or both signals of only a first class or of only a second class, (2) unrelated signals of both the first and second classes, or (3) related signals of both the first and second classes occurring in an improper sequence.

Other info:

Inventors: Cake, Arthur F. (Smithtown, NY, US)

Application Number: 495436
Filing Date: 1974-08-07
Publication_date: 1976-01-27
Assignee: Wagner Electric Corporation (Parsippany, NJ)
Primary Class(es): 180/270 340/457.1, 340/522, 340/523, 340/667
Other Classes:
US Patent Ref:

3742448

Jun, 1973

Motz

307/105.

Other Refs:
Primary Examiner: Hohauser, Herman J.
Assistant Examiner:
Attorney: Eyre, Mann & Lucas