Title: Selective signal receiver for use in telecommunication systems

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Claims: What is claimed is:

1. A selective signal receiver for use in telecommunication and particularly telephone systems wherein the time distances between zero crossings of the input voltage are measured with a counter which is controlled at a clock frequency higher than the signal frequency to be determined, and wherein the input voltage is evaluated as a signal only if the measured value lies between a lower and an upper count determining the bandwidth, wherein the improvement comprises a zero crossing detector coupled to provide a pulse each time the input voltage crosses zero, a zero crossing counter coupled to the zero crossing detector to count a predetermined number of said pulses indicating zero crossings of an input signal and the zero crossing counter providing a reset signal when that number is reached, a clock pulse counter coupled to start when the pulse including the first zero crossing occurs, where the lower count and the upper count of the clock pulse counter are chosen depending on the predetermined number of cycles, on the predetermined tolerances of the signal frequencies, and on permissible interference-voltage components.

2. A selective signal receiver according to claim 1, in which the predetermined number of cycles is chosen depending on the predetermined signal-to-noise ratio (e.g. 12 db).

3. A selective signal receiver for use in telecommunication and particularly telephone systems comprising a zero detector for receiving input voltages and providing zero-crossing pulses, first counter means coupled to the zero detector for measuring the time distances between selected zero crossings of an input voltage, second counter means coupled to receive signals from said zero detector and to receive clock signals at a frequency higher than the signal frequency to be determined, and means for evaluating the input voltage as a signal only if the measured time distance lies between a lower and an upper count, each measurement covering a predetermined number of cycles counted with the first counter means, the lower count and the upper count of the second counter being chosen depending on the predetermined number of cycles, on the predetermined tolerances of the signal frequencies, and on permissible interference-voltage components.

4. The invention as claimed in claim 3, in which the zero detector is responsive to the input signal to provide a spike in response to each zero crossing and the receiver includes means applying each said spike to the first counter to cause it to operate.

5. The invention as claimed in claim 4, and including flip-flop means responsive to a spike from said zero detector to enable the second counter to receive said clock signals.

Other info:

Inventors: Ball, Herbert (Stuttgart, DT)
Ohl, Wolf (Korntal, DT)

Application Number: 494287
Filing Date: 1974-08-02
Publication_date: 1976-01-27
Assignee: International Standard Electric Corporation (New York, NY)
Primary Class(es): 379/282
Other Classes:
US Patent Ref:

3537001	Oct, 1970	Friend	324/78.
3760269	Sep, 1973	Beeman	324/78.
3790720	Feb, 1974	Schartmann	179/84.

Other Refs:
Primary Examiner: Claffy, Kathleen H.
Assistant Examiner: Popek, Joseph
Attorney: Raden; J. B., Warner; D. P.