Title: Electronic solid state sensor image size control

Do you think this is a good invention? Vote now:

Votes so far: For:(0) Against:(0)
Claims: What is claimed is:

1. An electronic control system for generating scanning clock signals to control the scanning rate of a solid state sensor to read out the video information and control the image size reproduced on a TV monitor comprising:

a. s source of clock frequencies,

b. timing circuit means for providing a field synchronizing pulse output and a line synchronizing pulse output;

c. first counter circuit means coupled to said source of clock frequencies to provide a scanning clock signal of a predetermined frequency determined by a desired picture size,

d. delay circuit means coupled to said timing circuit means for delaying the field and line synchronizing pulses a predetermined time delay,

e. variable gate generator circuit means coupled to said delay circuit means and to said first counter means for gating a predetermined number of clock pulses to said solid state sensor corresponding to the size of the sensor array,

f. feedback circuit means coupled from said sensor to said variable gate generator circuit means for providing a feedback signal to turn off said variable gate at the end of said predetermined time.

2. The control system of claim 1 wherein said delay circuit means includes a first delay circuit coupled to the field sync output of said timing circuit means and a second delay circuit coupled through a divide by x counter to the line sync output of said timing circuit means for providing delayed line and vertical sync pulses to establish the position of the start of the horizontal and vertical scan respectively.

3. The control system of claim 2 wherein said variable gate generator circuit means includes:

a. a first flip-flop circuit coupled to the output of said first delay circuit for providing a vertical gate signal,

b. a first AND gate having a first input coupled to the output of said first flip-flop circuit and a second input coupled to the output of said second delay circuit for providing an output gate signal,

c. a second flip-flop circuit having a first input coupled to the output of said first AND gate for providing an output gate signal,

d. a second AND gate having a first input coupled to the output of said second flip-flop circuit and a second input coupled to the source of clock pulses for gating said clock pulses as long as a gate signal is generated by said second flip-flop circuit.

4. The control system of claim 3 wherein feedback circuit means are coupled from said sensor to said first and second flip-flop circuit means for providing a feedback signal to turn off said flip-flops at the end of the scan of the frame of said sensor.

Other info:

Inventors: Petrocelli, Edward A. (Sunrise, FL, US)
Louie, Anthony C. H. (San Diego, CA, US)

Application Number: 482393
Filing Date: 1974-06-24
Publication_date: 1976-01-27
Assignee: The United States of America as represented by the Secretary of the Navy (Washington, DC)
Primary Class(es): 348/240.99
Other Classes:
US Patent Ref:

3184539	May, 1965	Thomas	178/73.
3263028	Jul, 1966	Shanafelt et al.	178/7.
3637997	Jan, 1972	Peterson	178/7.
3713000	Jan, 1973	Driskell et al.	178/7.

Other Refs:
Primary Examiner: Griffin, Robert L.
Assistant Examiner: Saffian, Mitchell
Attorney: Sciascia; R. S., Rubens; G. J., Phillips; T. M.