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Primary Examiner: Lovell, C.
Assistant Examiner: Saba, W. G.
Attorney: Leitner, Palan & Martin

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Title: Process for forming monolithic semiconductor display

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Claims: What is claimed is

1. A method of fabricating a monolithic semiconductor display in a single crystal silicon substrate comprising:

epitaxially depositing on a plurality of selected regions of a surface of said silicon substrate a thin layer of an alloy of silicon to form a graded layer on each selected region having a crystal lattice constant substantially matching the crystal lattice constant of said silicon substrate at the boundary therebetween and having a crystal lattice constant substantially matching the crystal lattice constant of a preselected electroluminescent single crystal semiconductor material at a second surface;

thereafter epitaxially depositing a layer of said preselected electroluminescent semiconductor material on each of said thin layers;

forming a planar p-n junction in each of said layers of electroluminescent semiconductor material to form a plurality of light emitting diodes for said display; and

forming p-n junctions in said substrate and said graded epitaxial layer to form an active semiconductor component different from said light emitting diodes.

2. The method according to claim 1, wherein

said layer of electroluminescent material is selected from the group consisting of GaP, GaAs, and GaAsP.

3. The method according to claim 1 wherein said semiconductor component is formed to be a transistor.

4. The method according to claim 3 wherein said transistor is formed so as to be a part of the drive circuit for the electroluminescent layer.

5. The method of claim 1 wherein said thin layer is deposited to form a graded layer by vapor phase deposition and hydrogen reduction of a varying ratio of silicon tetrachloride and germanium tetrachloride.

6. The method of claim 1 wherein said thin layer is deposited by thermal decomposition of a varying ratio of silane and germanium tetrachloride.

7. The method of claim 1 wherein said thin layer deposited by thermal decomposition of a varying ratio of trichlorosilane and germanium tetrachloride.

8. The method of claim 1 wherein said silicon alloy is silicon and germanium in which the germanium concentration is zero at said substrate boundary and under 10 mole percent at said second surface.

Other info:

Inventors: Mason, Donald R. (Indialantic, FL, US)

Application Number: 369422
Filing Date: 1973-06-13
Publication_date: 1976-01-27
Assignee: Harris Corporation (Cleveland, OH)
Primary Class(es): 438/23 117/954, 117/955, 148/DIG26, 148/DIG67, 148/DIG72, 148/DIG85, 148/DIG119, 257/94, 257/190, 257/200, 257/E21.112, 257/E21.123, 438/37, 438/933
Other Classes:
US Patent Ref:

3275906	Sep, 1966	Matsukura et al.	317/234.
3309553	Mar, 1967	Kroemer	317/235.
3341376	Sep, 1967	Spenke et al.	148/175.
3433684	Mar, 1969	Zanowick et al.	117/106.
3433686	Mar, 1969	Marinace	148/175.
3473978	Nov, 1969	Jackson et al.	148/175.

Other Refs: Other References: Murray et al., "Lighting up in a Group" Electronics, Mar. 4, 1968, p. 104-110.
Blum et al., "Vapor Growth of Gap onto SiSubstrates" I.B.M. Tech. Discl. Bull., Vol. 13, No. 5, Oct. 1970, p. 1245.
Chang, I. F., "Fet-Bipolar Integration" Ibid., Vol. 14, No. 1, June 1971, p. 350-351.
Burmeister et al., "Epitaxial Growth of GaAs.sub.1.sub.-x O.sub.x on Germanium Substrates" Trans. Metallurgical Soc. Aime, Vol. 245, Mar. 1969, p. 565-569.