Title: Specialized digital computer with divided memory and arithmetic units

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Claims: What is claimed is:

1. A digital computer comprising:

memory means including a program store and additional storage means, said program store being provided with a timing input;

calculating means including a short-operation arithmetic unit and a long-operation arithmetic unit, said additional storage means being addressable by said program store for reading out instructions for said calculating means;

multiplexing means inserted between said additional storage means and said calculating means for selectively directing said instructions to said short-operation and long-operation arithmetic units under the control of said program store; and

clock means connected to said timing input for triggering said program store into correlated activation of said memory, multiplexing and calculating means.

2. A computer as defined in claim 1 wherein said additional storage means includes an on-off store with an output connection and with a transfer connection for data read out only from said short-operation arithmetic unit, said multiplexing means including an ancillary multiplexer with outside input connections and with a feedback branch from said output connection for selectively loading said short-operation arithmetic unit with external instructions and with the contents of said on-off store.

3. A computer as defined internal address channel originating at said claim 2 wherein said additional storage means further includes a buffer store with internal and external data-input channels, internal and external address channels, and internal and external data-output channels, said internal data-input channel originating at said calculating means, said originating at said program store, said internal data-output channel terminating at said multiplexing means, further comprising switchover means for alternately connecting said internal and said external data-input and address channels to said buffer store.

4. A computer as defined in claim 3 wherein said program store is provided with a selection channel for carrying branching instructions via said multiplexing means to said calculating means, further comprising changeover means for switching said timing input from said clock means to said internal data-input channel during emission of said branching instructions.

5. A computer as defined in claim 3 wherein said additional storage means further includes a read-only store for permanent data and a working store loadable from said internal data-input channel.

6. A computer as defined in claim 5, further comprising test means for systematically reading out the contents of said memory means to said calculating means for checking the performance of said stores.

7. A computer as defined in claim 6 wherein said test means comprises checking circuits connected to receive the contents of said program store and said read-only store for transmission to said calculating means via said multiplexing means, and address-indexing circuits connected to address inputs of said buffer, working and on-off stores.

Other info:

Inventors: Beriot, Alain (Paris, FR)

Application Number: 435593
Filing Date: 1974-01-22
Publication_date: 1976-01-13
Assignee: Thomson-CSF (Paris, FR)
Primary Class(es): 712/214 708/100
Other Classes:
US Patent Ref:

3348210	Oct, 1967	Ochsner	340/172.
3594732	Jul, 1971	Mendelson	340/172.
3697734	Oct, 1972	Booth et al.	235/164.
3760171	Sep, 1973	Wang et al.	235/156.

Other Refs:
Primary Examiner: Malzahn, David H.
Assistant Examiner:
Attorney: Ross; Karl F., Dubno; Herbert