Title: Control system for channel selection

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Abstract: A channel-selection control system for a frequency synthesizer type receiver which comprises: a frequency synthesizer (1); a plurality of switches (SW₁, SW₂) corresponding to channels having different broadcasting programs, respectively; a plurality of memories (ROM₁, ROM₂) associated with the respective switches (SW₁, SW₂) and each storing data signals (n) corresponding to broadcasting waves for one broadcasting program; a clock generator (CK) for producing clock pulses; a counter (CNT) adapted to count up by the clock pulses for producing address signals (m) for the memories; a comparator (COMP) for comparing a level value of a received signal outputted from said frequency synthesizer (1) with a preset reference level value; and a gate circuit (G₄) responsive to said comparator for preventing the clock pulses from being inputted to said counter (CNT) when the level value of the received signal is higher than the reference level value and for allowing the clock pulses to be inputted to the counter (CNT) when the level value of the received signal is lower than the reference level value; the data signal corresponding to the address signal produced from said counter (CNT), being read out from the memory (ROM₁, ROM₂) associated with the switch (SW₁, SW₂) selected; said read out data signal being supplied as a program signal to a programmable divider (PD) included in a PLL circuit of the frequency synthesizer (1).


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