Title: Digital frequency and phase lock loop

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Abstract: An improved jitter-free system for phase locking a locally generated signal with a received signal. The system provides and arithmetic synthesizer having a clock signal source which clocks a binary increment contained in an input register into the digital accumulator of the arithmetic synthesizer. A converter converts the output of the accumulator into the locally generated two-level signal whose frequency is determined by the average overflow rate of the accumulator. Logic including a phase detector compares the phases of the received and locally generated signals to produce an error signal whose magnitude is proportional to the phase difference between the received and locally generated signals and also an early/late phase changing periodic two level signal. A voltage-to-frequency (V/F) converter responds to said error signal to produce a first signal whose frequency is proportional to the magnitude of the error signal. An up/down counter means responds to the first signal to count at a rate equal to the frequency thereof and in a direction determined by the level of the periodic two level signal. The input register responds to the count in said up/down counter to vary the binary increment supplied to the accumulator to phase lock the received and locally generated signals.


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