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Title:
Logical circuit having bypass circuit
Abstract:
The logical circuit includes therein a logic block for performing a logical function. The logic block is connected with the selection circuit and the selection circuit selects the input signals thereto in response to the selection signal. The input terminals of the logic block are connected with a bypass circuit and the bypass circuit transmits the input signals applied to the input terminals of the logic block to the selection circuit. When the selection signal takes the selected one of the values, the input signals to the logic block are bypassed through the bypass circuit, without being passed through the logic circuit, and delivered as the outputs of the selection circuit.
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Inventors:
Oka, Yuichi (Hadano, JP)
Takiguchi, Yosimitsu (Hadano, JP)
Application Number:
06/022949
Filing Date: 1979-03-22 Publication_date: 1981-08-25 Assignee:
HITACHI LTD
Primary Class(es):
326/16
326/39
Other Classes:
G01R31/3185; H03K19/173; G01R31/28; H03K17/00; H03K19/00; H03K13/32
US Patent Ref:
| 3800233 | March, 1974 | Sauthier | 307/218 | ADJUSTABLE FREQUENCY PULSE GENERATOR | | 3924144 | December, 1975 | Hadamard | 324/73R | Method for testing logic chips and logic chips adapted therefor | | 4055754 | September, 1977 | Chesley | 324/73R | Memory device and method of testing the same | | 4176258 | November, 1979 | Jackson | 324/73R | Method and circuit for checking integrated circuit chips |
Other Refs:
Primary Examiner:
Zazworsky, John
Assistant Examiner:
Attorney:
Craig, And Antonelli
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