Title: Time dependent master reset

Abstract: A circuit for use with logic circuitry preventing any transients due to the power down and power up conditions of a power supply from causing any false or random operations of the logic. The turn off transients are suppressed by a reset signal to the logic circuitry generated by a timing module which is triggered when it detects an absence of AC signal over a specified period of time and is then held in a reset mode until the power supply voltage completely decays. The turn on transients are suppressed by a reset signal to the logic circuitry generated by the timing module, which is held in a reset mode until the power supply voltage has stabilized.

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Other info:

Inventors: Amacher, Gene L. (Cambridge, OH, US)
Dickover, Wesley D. (Thornville, OH, US)

Application Number: 037548
Filing Date: 1979-05-09
Publication_date: 1981-05-05
Assignee: NCR Corporation (Dayton, OH)
Primary Class(es): 327/198 326/14, 327/545, 361/89, 361/110, 361/187
Other Classes:
US Patent Ref:

3725675	Apr, 1973	Olsen	307/200.
4099068	Jul, 1978	Kobayashi et al.	307/200.
4122359	Oct, 1978	Breikss	307/200.
4151425	Apr, 1979	Cappa	307/200.

Other Refs:
Primary Examiner: Heyman, John S.
Assistant Examiner:
Attorney: Cavender; J. T., Hawk, Jr.; Wilbert, Litzinger; Jerrold J.