Title: Symbol decoding system

Abstract: A symbol decoding system incorporated in a NMOS/LSI chip generates asynchronously binary data in response to the scanning of bars and spaces of the symbol. The binary data may represent each bar or space as a numerical character, a margin or a center band of the symbol. The binary data also includes data identifying the bar or space and if the character generated is valid or invalid. Logic circuits generate a time delay period allowing the binary data to be generated asynchronously during the delay period. At the end of the delay period the binary data is outputted to a utilizing device for selecting the valid data from the data outputted by the decoding system.

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Inventors: Amacher, Gene L. (Cambridge, OH, US)
Naseem, Syed (Cambridge, OH, US)

Application Number: 043933
Filing Date: 1979-05-30
Publication_date: 1981-02-24
Assignee: NCR Corporation (Dayton, OH)
Primary Class(es): 235/462.07 250/568
Other Classes:
US Patent Ref:

3906203	Sep, 1975	Butulis	235/463.
4095096	Jun, 1978	Harada et al.	235/463.
4125765	Nov, 1978	Cowardin	235/463.
4146046	Mar, 1979	Dobras	235/463.
4146782	Mar, 1979	Barnich	235/463.

Other Refs:
Primary Examiner: Cook, Daryl W.
Assistant Examiner:
Attorney: Cavender; J. T., Hawk, Jr.; Wilbert, Lavin; Richard W.