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Title:
Integrated circuit
Abstract:
Four-pole circuit modules constructed in integrated injection logic (I.sup.2 L), each four-pole circuit having two signal inputs, a control input, and a signal output line. The signal output line is alternatively connected to one of the signal inputs by each of the two values of a bivalent control signal. This two-level logic can be used in multiplexers in which the four-pole circuits are successively arranged in two or more levels. A shift register composed of master-slave flipflops is obtained by connecting the signal output lines of a series of four-pole circuit modules to one of the signal input lines of the respective four-pole circuit modules and to a signal input line of the next four-pole circuit. Four-pole circuits can be arranged in a series with common control and different combinations of input signals in order to form an arithmetic member for one bit per input quantity. The four-pole circuit module is very suitable for computer-aided design (CAD), due to the advantageous location of the connection points and that small modifications in the geometry of the modular four-pole circuit modules implicitly realize additional inversion operations. The four-pole circuit module is modified to form a comparison circuit or an EXCLUSIVE-OR generator by other modifications.
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Inventors:
Le Can, Claude J. P. F. (Beek, NL) van den Beemt, Johannes A. C. (Nijmegen, NL)
Application Number:
847161
Filing Date: 1977-10-31 Publication_date: 1980-05-13 Assignee:
U.S. Philips Corporation (New York, NY)
Primary Class(es):
326/52
257/575, 326/100, 377/73
Other Classes:
US Patent Ref:
| 3235840 | Feb, 1966 | Sturm | 307/243. | | 3551900 | Dec, 1970 | Annis | 307/244. | | 3601631 | Aug, 1971 | Miller | 307/209. | | 3731073 | May, 1973 | Moylan | 307/207. | | 3855484 | Dec, 1974 | Essen et al. | 357/92. | | 3992703 | Nov, 1976 | Luisi et al. | 307/243. | | 3993918 | Nov, 1976 | Sinclair | 357/92. | | 4053793 | Oct, 1977 | Ernst et al. | 307/207. | | 4056736 | Nov, 1977 | Blatt | 307/207. | | 4084105 | Apr, 1978 | Teranishi et al. | 307/207. |
Other Refs:
Other References:
Robbins; "MTL Exclusive OR circuit"; IBM Tech. Discl. Bull.; vol. 19, No. 6, p. 2077; 11/1976. _ Higby, Jr.; "Parity Check Circuit"; IBM Tech. Discl. Bull; vol. 1, No. 6; pp. 9-10; 4/1959. _ |