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Title:
Semiconductor device with multi-layered metalizations
Abstract:
There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.
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Inventors:
Aoyama, Masaharu (Yokohama, JP) Hiraki, Shunichi (Yokohama, JP) Yonezawa, Toshio (Yokosuka, JP)
Application Number:
831873
Filing Date: 1977-09-09 Publication_date: 1980-05-06 Assignee:
Tokyo Shibaura Electric Co., Ltd. (JP)
Primary Class(es):
438/625
29/847, 257/E21.309, 257/E21.311, 257/E21.582, 438/648, 438/674, 438/739, 438/754, 438/945
Other Classes:
US Patent Ref:
Other Refs:
Primary Examiner:
Tupman, W. C.
Assistant Examiner:
Attorney:
Finnegan, Henderson, Farabow, Garrett & Dunner
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