Title: VMOS transistor and method of fabrication

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Abstract: A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction. The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.


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