Title: ROM memory cell with 2.sup.n FET channel widths

Abstract: An FET read-only memory cell capable of storing more than one bit per cell. The channel geometry of the FET cell is selected to provide an electrical output that is characteristic of a predetermined combination of bits. For example, the FET channel width can be selected to provide one of 2.sup.n predetermined output voltage values which correspond to the 2.sup.n possible arrangements of n bits. The read function utilizes 2.sup.n -1 sense amplifiers, which are connected to the FET. Each sense amplifier is selectively activated at a separate one of 2.sup.n -1 voltage levels which is intermediate two adjacent values of the 2.sup.n output voltages. The collective outputs of the sense amplifiers drive a logic circuit for decoding the values of the n data bits represented by the FET channel width.

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Other info:

Inventors: Craycraft, Donald G. (Spring Valley, OH, US)

Application Number: 962572
Filing Date: 1978-11-20
Publication_date: 1980-03-04
Assignee: NCR Corporation (Dayton, OH)
Primary Class(es): 365/104 257/E27.102, 365/45
Other Classes:
US Patent Ref:

3656117	Apr, 1972	Maley et al.	365/104.
4054864	Oct, 1977	Audaire et al.	365/184.
4085459	Apr, 1978	Hirabayashi	365/184.

Other Refs:
Primary Examiner: Hecker, Stuart N.
Assistant Examiner:
Attorney: Cavender; J. T., Dalton; Philip A.