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Title:
Safety circuits for coupling laddics in cascade
Abstract:
A coupling arrangement for coupling laddics in cascade comprises an emitter follower transistor circuit arranged so that the output impedance of the transistor restricts the rise and fall times in the mmf of the laddic output winding. The effect is to reduce the risk of spurious reset signals being generated in the output winding of sufficient amplitude to reset the next laddic in the cascade.
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Inventors:
Keats, Albert B. (Dorchester, GB) Leggett, Dudley W. (Weymouth, GB)
Application Number:
911631
Filing Date: 1978-06-01 Publication_date: 1980-03-04 Assignee:
United Kingdom Atomic Energy Authority (London, GB2)
Primary Class(es):
365/91
365/206
Other Classes:
US Patent Ref:
Other Refs:
Other References:
Bell System Technical Journal--vol. 38, No. 1, 1959, pp. 45-72. British Communications & Electronics--Mar. 1962, pp. 180-184. |