Title: Bipolar monolithic integrated circuit memory with standby power enable

Abstract: A bipolar monolithic integrated circuit memory wherein a standby power enable circuit includes a pair of transistors arranged in an active pullup configuration for electrically coupling or decoupling a memory array addressing section of such memory and a ground bus selectively in accordance with a standby enable signal. The standby power enable circuit is connected between the addressing section and the ground bus to reduce the standby power required by the memory. One of the pair of transistors in the active pullup configuration is an N-P-N transistor having a Schottky barrier diode clamp formed as a part of the monolithic integrated circuit memory. The use of such a transistor in the standby power enable circuit ensures rapid switching operation of the memory.

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Inventors: Schmitz, Charles R. (Cupertino, CA, US)

Application Number: 909334
Filing Date: 1978-05-25
Publication_date: 1979-11-13
Assignee: Raytheon Company (Lexington, MA)
Primary Class(es): 365/96 326/19, 326/90, 365/189.11, 365/225.6, 365/227, 365/229, 365/230.01
Other Classes:
US Patent Ref:

3599182	Aug, 1971	Henle	365/227.
3631410	Dec, 1971	Velasco	340/173.
3680061	Jul, 1972	Arbab et al.	365/227.
3688280	Aug, 1972	Ayling et al.	365/227.
3703710	Nov, 1972	Kubo et al.	365/227.
3790817	Feb, 1974	Dobkin	307/317.
3806898	Apr, 1974	Askin	365/222.
3859637	Jan, 1975	Platt et al.	365/227.
3867644	Feb, 1975	Cline	307/317.
3979611	Sep, 1976	Payne et al.	307/317.
3979735	Sep, 1976	Payne	340/173.
3986045	Oct, 1976	Lutz	307/317.
4023148	May, 1977	Huber et al.	340/173.
4038564	Jul, 1977	Hakata	307/205.

Other Refs:
Primary Examiner: Hecker, Stuart N.
Assistant Examiner:
Attorney: Sharkansky; Richard M., Pannone; Joseph D.