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Primary Examiner: Anagnos, Larry N.
Assistant Examiner:
Attorney: Finnegan, Henderson, Farabow & Garrett

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Title: CMOS FET device with abnormal current flow prevention

Abstract: A CMOS FET device which comprises an N type semiconductor substrate; a P type well layer formed in the N type semiconductor substrate; a p-channel type MOS transistor provided in the N type semiconductor substrate; an n-channel type MOS transistor formed in the P type well layer; and a noise-absorbing capacitor provided at the input or output terminal of the MOS transistor or at a power supply section.

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Inventors: Satou, Kazuo (Yokohama, JP)
Ueno, Mitsuhiko (Fujisawa, JP)
Suzuki, Yasoji (Kanagawa, JP)

Application Number: 908661
Filing Date: 1978-05-23
Publication_date: 1979-09-18
Assignee: Tokyo Shibaura Electric Co., Ltd. (JP)
Primary Class(es): 327/310 257/372, 257/E27.063, 326/21, 327/552
Other Classes:
US Patent Ref:

3601625	Aug, 1971	Redwine et al.	307/304.
3636385	Jan, 1972	Koepp	307/200.
3665218	May, 1972	Andrew, Jr.	307/200.
3712995	Jan, 1973	Steudel	307/304.
3862441	Jan, 1975	Nabetani et al.	307/304.
3934159	Jan, 1976	Nomiya et al.	307/304.
3955210	May, 1976	Bhatia et al.	357/42.
3967295	Jun, 1976	Stewart	307/304.
4015147	Mar, 1977	Davidson et al.	357/42.

Other Refs: Other References: Dennehy, "Non-Latching Integrated Circuits"; RCA Technical Notes (pub.) TN No.: 876; 2/12/71; 4 pp.
Staples, "Electrical Noise Spike Suppression"; IBM Tech. Discl. Bull.; vol. 15, No. 10, p. 3208; 3/73.
Clapper, "Bandpass Filter Using Differential Amplifier", IBM Tech. Discl. Bull.; vol. 14, No. 3, pp. 815-816, 8/71.