Title: Permutation memories

Abstract: A permutation memory comprises an input control means for decoding, having plurality L of inputs for an L-bit binary number, and a plurality 2.sup.L of outputs. Means are connected to the decoding means, for initiating the read-in of the L-bit number. Means are provided for applying an input signal. A first plurality of 2.sup.L of normally open switching means are connected to the 2.sup.L outputs of the decoding means and to the signal applying means. A plurality of 2.sup.L of means are connected to the switching means, for storing a charge when a specific switching means, connected to a corresponding charge storing means, is in a closed condition. A second plurality 2.sup.L of switching means are connected to the first plurality of switching means and to the charge storing means. An output control means, connected to the second plurality of switching means, reads out the states of the 2.sup.L charge-storing means, as to the amount of charge in each. Means are connected to the read-out means, for initiating the read-out.

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Other info:

Inventors: Whitehouse, Harper J. (San Diego, CA, US)
Speiser, Jeffrey M. (San Diego, CA, US)

Application Number: 835765
Filing Date: 1977-09-22
Publication_date: 1979-08-07
Assignee: The United States of America as represented by the Secretary of the Navy (Washington, DC)
Primary Class(es): 365/45 348/403.1, 365/183
Other Classes:
US Patent Ref:

3909806	Sep, 1975	Uchida	365/45.
3914748	Oct, 1975	Barton et al.	365/45.
4007446	Feb, 1977	Elmer et al.	365/183.
4092734	May, 1978	Collins et al.	365/183.

Other Refs:
Primary Examiner: Ruggiero, Joseph F.
Assistant Examiner:
Attorney: Sciascia; Richard S., Johnston; Ervin F., Stan; John