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Title:
Fet-teld combination with capacitively coupled output electrode means
Abstract:
A field effect transistor (FET) is connected in series to a transferred electron logic device (TELD), the TELD being a non-linear load resistor for the FET. The current thresholding property of the TELD and the saturation characteristics of the FET are utilized to produce an output pulsed signal of substantial voltage gain with fast rise time and short pulse width. An output electrode is capacitively coupled to the TELD to provide an output pulsed signal of alternating polarity for direct interconnection of devices in cascaded circuits.
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Inventors:
Upadhyayula, Lakshminarasimha C. (East Windsor, NJ, US)
Application Number:
816692
Filing Date: 1977-07-18 Publication_date: 1979-03-20 Assignee:
RCA Corporation (New York, NY)
Primary Class(es):
327/581
257/E27.003
Other Classes:
US Patent Ref:
Other Refs:
Other References:
IEEE Journal of Solid State Electronics, vol. SC-7, No. 3, Jun. 1972, pp. 231-237, "A Most Inverter with Improved Switching Speed", by J. Kooman & Akker. IEEE Journal of Solid State Circuits - "Gunn Device Gigabit Rate Digital Microcircuits" by K. Mause, A. Schlachetzki, E. Hesse and H. Salow; pp. 2-11, Feb. 1975. Electronic Letters, "Integration of GaAs MESFETS and Gunn Elements in a 4-Bit Gate Device" by N. Hashizume and S. Kataoka; pp. 370-372, Jul. 1976, vol. 12, No. 15. |