Title: Manufacturing method of semiconductor devices

Abstract: A manufacturing method of semiconductor device having a single layer or multilayer of polycrystalline semiconductor including doped impurity is provided which comprises a step of forming a first polycrystalline semiconductor layer with doped impurity on a semiconductor substrate and another step of forming a second polycrystalline semiconductor layer without doped impurity on the first polycrystalline semiconductor layer. The manufacturing method of the invention provides excellent MOS FET's in the semiconductor device of which the threshold voltage varies little. High reliable semiconductor device may further be manufactured with a high yield.

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Inventors: Harada, Nozomu (Yokohama, JP)
Kubota, Nobuhisa (Yokohama, JP)

Application Number: 813464
Filing Date: 1977-07-07
Publication_date: 1979-03-06
Assignee: Tokyo Shibaura Electric Co., Ltd. (Kawasaki, JP)
Primary Class(es): 438/393 148/DIG25, 148/DIG51, 148/DIG53, 148/DIG117, 148/DIG122, 257/236, 257/313, 257/E21.316, 257/E21.457, 257/E21.575, 257/E27.085, 257/E27.103, 427/248.1, 427/255.
Other Classes:
US Patent Ref:

3460007	Aug, 1969	Scot, Jr.	317/59.
3651385	Mar, 1972	Kobayash	317/59.
3873371	Mar, 1975	Wolf	427/85.
3969168	Jul, 1976	Kuhn	427/85.
4001861	Jan, 1977	Carner	357/59.

Other Refs:
Primary Examiner: Esposito, Michael F.
Assistant Examiner:
Attorney: Oblon, Fisher, Spivak, McClelland & Maier