Title: Semiconductor process using lapped substrate and lapped low resistivity semiconductor carrier

Abstract: A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.

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Inventors: Henry, Raymond (Paris, FR)
Bouvet, Jean-Victor (Paris, FR)

Application Number: 731213
Filing Date: 1976-10-12
Publication_date: 1979-02-27
Assignee: Thomson-CSF (Paris, FR)
Primary Class(es): 438/108 257/626, 257/720, 257/733, 257/E23.101, 257/E23.184, 438/459
Other Classes:
US Patent Ref:

3343255	Sep, 1967	Donovan	357/49.
3445303	May, 1969	Engbert	357/56.
3559282	Feb, 1971	Lesk	357/81.
3609474	Sep, 1971	Vincen, Jr.	357/81.
3689993	Sep, 1972	Tolar	357/81.
3775200	Nov, 1973	DE Nobel et al.	357/56.
3908187	Sep, 1975	Sheldon et al.	357/81.
4035830	Jul, 1977	Kim	357/81.

Other Refs: 22320818077288631199929631120488112633812810101295892

Dec, 1974	FR.
Jan, 1959	GB.
Mar, 1961	GB.
May, 1965	GB.
Jul, 1968	GB.
Sep, 1968	GB.
Jul, 1972	GB.
Nov, 1972	GB.

Primary Examiner: Larkins, William D.
Assistant Examiner:
Attorney: Oblon, Fisher, Spivak, McClelland & Maier