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Title:
Inverter with improved load line characteristic
Abstract:
An insulated gate field effect transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter. Alternate embodiments are disclosed directed to an all N-channel inverter, an all P-channel inverter, and a complementary inverter consisting of a P-channel load device and an N-channel active device.
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Inventors:
De la Moneda, Francisco H. (Reston, VA, US) Kotecha, Harish N. (Manassas, VA, US)
Application Number:
851660
Filing Date: 1977-11-15 Publication_date: 1979-02-13 Assignee:
International Business Machines Corporation (Armonk, NY)
Primary Class(es):
438/234
257/E21.033, 257/E21.631, 257/E27.061, 257/E27.062, 438/276, 438/291, 438/294
Other Classes:
US Patent Ref:
Other Refs:
Primary Examiner:
Tupman, W.
Assistant Examiner:
Attorney:
Hoel; John E.
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