Title: Stamped lead frame for semiconductor packages

Abstract: A stamped, 40-lead ceramic dual-in-line package (Cer-Dip) frame is disclosed. Increased usage and lowered costs of large scale, integrated circuits (LSI) for microprocessor and similar applications has created a demand for precision ceramic packaging of the forty-lead dual-in-line type that is adapted for automated chip insertion in high-volume and at a low cost. The present invention meets this need with a stamped lead frame wherein the longest and most fragile leads are held in precise spatial relation by means of break-off tabs. After embedment of the leads on the ceramic substrate with a glass composition, the tabs are broken and removed. Forming, scoring and bending of the tabs are carried out as an integral part of the progressive stamping operation. Lead frames according to the invention replace much more expensive etched parts. The invention may be applied in a variety of packages.

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Inventors: Frusco, John M. (Scotch Plains, NJ, US)

Application Number: 842322
Filing Date: 1977-10-14
Publication_date: 1979-01-30
Assignee: Plessey Incorporated (Montvale, NJ)
Primary Class(es): 257/670 29/827, 257/E23.043, 361/813
Other Classes:
US Patent Ref:

3404319	Oct, 1968	Tsusi et al.	357/70.
3665256	May, 1972	Goun et al.	357/70.
3685137	Aug, 1972	Gardiner	357/70.
3751724	Aug, 1973	McGrath et al.	357/70.
3783346	Jan, 1974	Schierz	357/70.
3930114	Dec, 1975	Hodge	357/70.
3986334	Oct, 1976	Harper	357/70.
3986335	Oct, 1976	Harper	357/70.
4065625	Dec, 1977	Iwai et al.	357/70.
4084312	Apr, 1978	Kirk et al.	357/70.

Other Refs: 1429358

Mar, 1976	GB

Primary Examiner: James, Andrew J.
Assistant Examiner:
Attorney: Burke; James J.