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Title: Integrated DDC memory with bitwise erase

Abstract: This relates to a monolithic dual-dielectric cell (DDC) memory array with a DDCFET matrix. The substrate zones of these DDCFETs are inserted into a substrate body having islands for decoder logic and potential selection integrated MISFET circuits. These circuits provide potentials to bitwise write, erase or read the matrix.


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Other info:


Inventors: Adam, Fritz G. (Freiburg i. Br, DE, US)

Application Number: 804685
Filing Date: 1977-06-08
Publication_date: 1978-12-19
Assignee: ITT Industries, Inc. (New York, NY)
Primary Class(es): 365/184 257/E27.103, 365/189.01, 365/218, 365/230.01
Other Classes:
US Patent Ref:
3618051Nov, 1971Oleksiak340/173.
3733591May, 1973Cricchi340/173.
3971001Jul, 1976Lodi340/173.

Other Refs:
Primary Examiner: Hecker, Stuart N.
Assistant Examiner:
Attorney: O'Halloran; John T., Van Der Sluys; Peter C.