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Primary Examiner: Anagnos, Larry N.
Assistant Examiner:
Attorney: Woodward; Gail W.

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Title: MOS output buffer circuit with feedback

Abstract: A PMOS output buffer circuit permits interfacing directly with TTL, CMOS, and NMOS. A feedback circuit incorporated into the buffer acts to limit the drive current for negative potential output excursions. The feedback circuit is sensitive to device parameters that vary with processing so that the output characteristics can be set independently of process variables.

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Other info:

Inventors: Khaitan, Basant K. (San Jose, CA, US)

Application Number: 771145
Filing Date: 1977-02-23
Publication_date: 1978-06-20
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Class(es): 326/70 326/34, 326/71, 326/83, 330/269
Other Classes:
US Patent Ref:

3648071	Mar, 1972	Mrazek	307/237.
3700981	Oct, 1972	Masuhara	307/205.
3736522	May, 1973	Padgett	330/35.
3980898	Sep, 1976	Priel	307/208.
4019068	Apr, 1977	Bormann	307/209.
4032800	Jun, 1977	Droscher et al.	307/DIG.
4037114	Jul, 1977	Stewart et al.	307/209.

Other Refs: 2,250,554

Apr, 1974	DT

Other References: Gardner, "FET Off-Chip Driver Clamping", IBM Tech. Discl. Bull., vol. 16, No. 1, pp. 275-276, 6/1973.